JPS634731B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-flop circuit composed of insulated gate field effect transistors (MOS-FETs).

This type of conventional flip-flop circuit has a first
As shown in Figures a and b, each of them was composed of, for example, six N-channel type MOS-FFTs. That is, T ₁ , T ₂ and T ₃ and T ₄ are NOR-gate connected enhancement type transistors, T ₅ and T ₆ are enhancement type load transistors, and T' ₅ and T' ₆ are depletion type load transistors.

As is well known, the operation of the flip-flop circuit shown in FIG. 1 consumes the power supply current _IDD whether the output Q is at a high or low level, and this consumption maintains the output Q level stably. , and the reversibility of the output Q is not necessarily uniform, and furthermore, the reversal speed is not sufficiently high.

The present invention was made in view of the above circumstances, and
To provide a flip-flop circuit that can realize a drastic reduction in current consumption, uniform inversion characteristics, and high-speed inversion operation by adding two state-holding transistors that use gate capacitance to hold the state. It is something.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 2, transistors T ₁ to _{T 8} are, for example, N-channel enhancement type MOS-FETs formed on the same semiconductor substrate, and T ₁ , T ₃ , T ₆ , and T ₈ are drive transistors,
T ₂ and T ₅ are state holding transistors added to hold the state using gate capacitance,
T ₄ and T ₇ are state holding transistors, and the drains and sources of transistors T ₃ and T ₄ are connected to each other to form a NOR gate, and similarly, transistors T ₇ and T ₈ are also connected to each other to form a NOR gate. It is connected.

The sources of transistors T ₃ , T ₄ , T ₇ , and T ₈ are connected to the substrate potential V _SS (ground potential in this example), and the drains of transistors T ₃ and T ₄ are connected to the output terminal Q. The drains of transistors T ₇ and T ₈ are connected to the output terminal Q, and the transistor T ₃
The gate of the transistor T4 is connected to the set input terminal S, the gate of the transistor _T4 is connected to the output terminal Q, the gate of the transistor _T7 is connected to the output terminal, and the gate of the transistor _T8 is connected to the reset input terminal R.

On the other hand, transistors T ₁ and T ₂ have drains mutually,
They are OR-connected by connecting their sources together, and the transistors T ₅ and T ₆ are also OR-connected by connecting their drains and sources together. The drains of transistors T ₁ , T ₂ , T ₅ , and T ₆ are connected to the power supply terminal V _DD
(V _DD potential), the sources of transistors T ₁ and T ₂ are connected to the output terminal, the sources of transistors T ₅ and T ₆ are connected to the output terminal Q, the gate of transistor T ₁ is connected to the reset input terminal R, and the gate of transistor T ₂ is connected to the output terminal, the gate of the transistor _T5 is connected to the output terminal Q, and the gate of the transistor _T6 is connected to the set input terminal S.

Next, the operation shown in FIG. 2 will be explained. When the set input terminal S is now at the "1" level (V _DD ) and the reset input terminal R is at the "0" level (V _SS ), the transistor
T ₃ and T ₆ are on, T ₁ and T ₈ are off, and the output terminal becomes "0", so T ₂ and T ₇ are off, so the output terminal Q becomes "1" and T ₄ is on. becomes. Therefore, current flows in the path of the power terminals V _DD →T ₆ and T ₄ →V _SS potential, and the output terminal Q is charged up and the output terminal is discharged.

Following this active state,
When the set input terminal S reaches the "0" level, the circuit enters the holding state. That is, in this holding state, T ₃ and T ₆ are inverted to OFF, but due to the charge held at the gate of T ₅ , the output terminal Q is in the "1" state, T ₄ is on, and the output terminal is "0". The level state is maintained for a practically sufficient period of time. Therefore,
The power consumption current during this holding period is extremely small and consists only of transistor leakage current.

Next, if a "1" level is applied to the reset input terminal R, T ₈ and T ₁ are turned on and the charge of T ₅ is immediately released through T ₈ , so the output terminal Q immediately becomes "0". At the same time, _T4 is turned off and the output terminal is immediately inverted to "1" level. That is, the reversing operation speed is sufficiently high. Then, due to the "1" level at the output terminal, _T7 is turned on and current flows through the path of the power supply terminals V _DD -> T ₁ and T ₇ -> V _SS potential, and the output terminal is charged up and the output terminal Q is discharged.

Therefore, when the reset input terminal R becomes "0" level after this, T ₁ and T ₈ are turned off and the circuit enters the holding state, but due to the charge of T ₂ , the output terminal becomes "1" level state and Since _T7 is on and the output terminal Q is held at the "0" level for a long period of time, the power consumption current is extremely small. Also, when the reset input as mentioned above becomes “1”,
The level reversal time of the output Q due to the discharge of T ₅ and the T ₂ that was charged in the previous holding state when the set input became “1”.
The level inversion time of the output due to discharge can be made almost equal by configuring the characteristics of T ₅ and T ₂ to be the same, and the above circuit has very good uniformity of inversion operation.

In addition, in the so-called prohibited state where "1" level is applied to both the set input terminal S and the reset input terminal R,
The level at the output terminal Q is approximately determined by the impedance ratio between T ₆ and T ₈ , and the level at the output terminal is approximately determined by the impedance ratio between T ₁ and T ₃ .

Although the above embodiment uses an N-channel transistor, it is also possible to use a P-channel transistor.

As described above, according to the flip-flop circuit of the present invention, by adding a transistor for holding charge using a gate capacitance to maintain the state of the circuit, current consumption can be drastically reduced, inversion operation can be made uniform, and It is possible to realize high-speed inversion operation, and it is extremely convenient for application to integrated circuits.

[Brief explanation of the drawing]

1A and 1B are circuit diagrams showing conventional flip-flop circuits, and FIG. 2 is a circuit diagram showing an embodiment of the flip-flop circuit according to the present invention. T ₁ to T ₈ ... Transistor, S ... Set input terminal, R ... Reset input terminal, V _DD ... Power supply terminal,
Q... Output end.

Claims (1)

[Claims] 1 In a flip-flop circuit composed of a plurality of enhancement type insulated gate field effect transistors of the same channel type, the drains of transistors _{T 1 ,} T ₂ , _{T 5 ,} and T ₆ among the eight transistors T 1 to T 8 The source sides of transistors T ₃ , T ₄ , T ₇ , T ₈ are connected to the substrate potential terminal of the transistors, and the source sides of transistors T ₁ , T ₂ and transistors are connected to the power supply voltage terminal.
Connect the drain sides of T ₃ and T ₄ and make the connection point the output terminal, connect the source sides of transistors T ₅ and T ₆ and the drain sides of transistors T ₇ and T ₈ , and output the connection point. Let the end be Q, and the transistor T ₃ ,
The gate of T ₆ is connected to the set input terminal S, the gates of transistors T ₁ and T ₈ are connected to the reset input terminal R, the gates of transistors T ₂ and T ₇ are connected to the output terminal, and the gates of transistors T ₄ and T 8 are connected to the output terminal. A flip-flop circuit characterized in that the gate of _T5 is connected to the output terminal Q.