JPS634743A - Biphase modulation wave demodulator - Google Patents

Abstract

PURPOSE:To accurately reproduce a burst data even with a short preamble length by preparing an independent reproducing clock source corresponding to each burst and selecting and using a clock adjusted in advance at every arrival of each burst. CONSTITUTION:The output signals of clock phase adjusting circuits 191-19n are inputted respectively to a code discrimination circuit 7 and a sample holding circuit 8 via a switch 20. The switch 20 is subjected to its position control by a signal fed to a control signal input terminal 21. Then each output of the clock phase adjusting circuits 191-19n, at the arrival of a relevant burst, is connected to code discrimination circuit 7 and the sample holding circuit 8, its branch signal is inputted to a phase comaparator 14, the phase is compared with that of the clock of a clock recovery circuit 13, whose output phase is controlled by the phase comparison information of the timing when the burst clock is reproduced correctly.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is a decision feedback loop-type two-phase modulation system that reproduces each modulated signal from a group of two-phase modulated waves received in a burst form.
The present invention relates to a phase modulation wave demodulator.

[Conventional technology]

An example of a conventional decision feedback loop type two-phase modulated wave demodulator is shown in FIG. 6 and will be described.

In the figure, 1 is an input terminal to which a two-phase phase modulated wave is applied, 2, 3 and 13 are phase comparators and clock regeneration circuits to which branch signals from input terminal 1 are input, and 5 and 6 are phase comparators. 2. A low-pass filter that transmits each of the output signals in 3 to a low frequency range, and 8 is this low-pass filter 5.
7 is a sign determination circuit that judges the output signal of the low-pass filter 6 at the timing of the clock; 9 is the output of the sample and hold circuit 8; the output and the sign; A multiplier that multiplies the output of the determination circuit 7, 10 a loop filter that transmits the output signal of this multiplier 9, 11 a voltage controlled oscillator whose oscillation frequency is controlled by the output voltage of this loop filter 10, and 4 this voltage. The phase of one of the signals obtained by branching the output of the controlled oscillator 11 into two is π/2(r
ad) It is a phase shifter that shifts the phase.

Then, the output of the sign determination circuit 7 is set as the output terminal 12, and 2
It is configured to reproduce a modulated signal from a phase modulated wave.

Next, the operation of the circuit shown in FIG. 6 will be explained.

First, a received two-phase phase modulated wave is input to input terminal 1, and this input signal is branched into three and input to phase comparator 2, phase comparator 3, and clock recovery circuit 13, respectively. Then, the input wave input to the phase comparator 3 is transmitted to the phase shifter 4.
When the phase is detected by the output wave (reference carrier wave) of
Therefore, the above-mentioned 2 is output through the low-pass filter 6.
Obtain the demodulated signal of the phase modulated wave.

Now, for easy explanation, a two-phase phase modulated wave will be temporarily expressed by the following equation (1).

S (t) = As(TI (ω, t + rk(t
) + θi ) ---= (1) In this equation (1), A is the amplitude of the input wave, ωS is its central angular velocity, θi is its initial phase, sb, and k (t) represents the modulation signal. k(t) = 0 depending on the logic %01 or logic %11 of the modulation signal that changes every clock period.
, k (L)=1.

On the other hand, the output signal of the phase shifter 4 is expressed by the following equation (2).

Rt(t) = 2 s stone (ωrt+00)...
(2) In this equation (2), 2 is the amplitude of the phase shifter output signal.

ω1 is its central angular velocity, θ. is the initial phase.

The output signal of the phase comparator 3 is expressed as the product of the above two signals.

Therefore, the output signal of this phase comparator 3 is K pt
(t), this is given by the following equation (3).

KPI(t)=5(t)X Rz(t)=Az((ω
S-ω, )1+(θ1-00)+πk(t) )-Ac
os((ωS+ωr) t + (θi+θo)+gk
(t) )・・・・・・・・・・・・・・・・・・ (
3) Furthermore, in this equation (3), ω8=ωr,
Furthermore, assuming that the high frequency component of the above equation (3) is removed by the low-pass filter 6, this low-pass filter 6
The output signal KLz (t) is given by the following equation (4).

K L 2 (t) = A cnq (π k
(t) 100 amount -θG) -・----
-------(4) In this equation (4), θlζθ.

Then, KL2(t) is approximately −A when k(t)=O
(V), and still almost A(V
It becomes l.

Further, in the sign determination circuit 7, KLz<0
(V), set its output logic to 10", - and
If KLI >o (v), its output logic is 11″
If this is done, an output signal corresponding to the original modulation signal will be obtained at the output terminal 12.

On the other hand, the output signal of the phase comparator 2 is given by the following equation (5), similar to the output signal of the ninth-order comparator 3 shown above.

Kpl(t)=S(t)XR+(t)・
・・・・・・・・・・・・ (5) Here, Rt(t)
is the output signal of the voltage controlled oscillator 11, and the phase is advanced by π/2 (rad) from the output signal of the phase shifter 4, as shown in the following equation (6).
is given by

Rt (t) = 23tI (ωrt+π/2+00)
...... River... (6) Therefore, if the output signal of the low-pass filter 5 is KLI (t), it is K Ll (t) = Az (rk (t) - π/2 + θ
It is given by i-θ0.

Now, for convenience of explanation, it is assumed that the sample and hold circuit 8 is omitted and the signal given by the above equation (7) is directly applied to one side of the multiplier 9. Further, the same logical signal as the signal obtained at the output terminal 12 shown above is branched and input to the other input of the multiplier 9. and,
If the former signal is the signal at terminal I, and the latter signal is the signal at terminal ■, then this multiplier 9 outputs the signal at terminal I as it is to its output terminal when the logic of the signal at inner H is 10''. Further, when the logic of the signal at terminal H is 11'', the sign of the signal at terminal l is inverted and output to that output terminal.

In other words, regardless of the logic of k(t), the output terminal of the multiplier 9 has e0=A(θi−θ.).
It is clear from the logic of the output terminal 12 and the above equation (7) that a voltage of (8) is output.

In the above equation (8), eo is a signal generally referred to as a phase error voltage between the input signal wave of the input terminal 1 and the output signal wave of the voltage controlled oscillator 11, which is passed through the loop filter 10 to the frequency control terminal of the voltage controlled oscillator 110. is input.

The output frequency of this voltage controlled oscillator 11 is controlled in accordance with this phase error voltage.

That is, θi−θ. When the value of is positive, the output frequency is increased, and when it is negative, the output frequency is decreased.

As a result, the angular frequency ω1 of the output of the voltage controlled oscillator 11 is the central angular frequency ω of the input wave applied to the input terminal 1.
6 under certain conditions. Also, θ.

is approximately equal to θi. In other words, the previously assumed ω8
=ω1. Also, θ. ζθl is satisfied (this is referred to as the reference transport being regenerated).

In the end, the phase comparator 2, the low-pass filter 5, and the loop filter 1 except for the sample-and-hold circuit 8 and the multiplier 9
0 and the voltage controlled oscillator 11 form a generally well-known phase-locked loop (PLL), and the multiplier 9 added here performs two-phase phase modulation on the signal wave input to the input terminal 1. Therefore, when this modulation component is superimposed on the error voltage t0, it serves to cancel out the error voltage t0.

Next, the roles of the sample hold circuit 8 and the clock recovery circuit 13 and the operation of the sign determination circuit 7, which were omitted earlier, will be explained in more detail.

In the previous explanation, for the sake of simplicity, we will use a diagram in which the modulated signal k(t) is set to either logic "0" or 'IN' for each symbol clock unit, that is, a logical example of the modulated signal and the corresponding demodulated output waveform. A binary signal as shown by (凰) in FIG. 7, which shows an example, was used, and the modulated wave resulting from this was defined as the above equation (1).

The occupied frequency band of equation (1) obtained by binary phase modulation using such a signal is extremely wide, which is not practical.

Therefore, in general, the modulated wave is transmitted after band-limiting the modulated signal k(1) or band-limiting the modulated wave S(t), and is applied to the input terminal 1. As a result, the demodulated waveform of the low-pass filter 6 in FIG.
The state shown in FIG. 7(b) corresponds to FIG. 7(a).

Actually, since noise is added in the transmission path, the voltage waveform of the noise component is also superimposed on the waveform of FIG. 7(b).

Now, in the previous explanation, the waveform shown in FIG. 7(b) is input to the sign determination circuit 7, and if the value KL2 is
It was stated that if ≦0, the output is set to logic "0", and if Kt > 0, the logic is set to %11, but KL! If noise is superimposed on the waveform shaped as shown in Figure 7(b), for example, in the interval from T to T1 (in this interval = 1) in Figure 7(-). Corresponding sign determination circuit 7 from T o/ to T ' in FIG. 7(b)
The output logic of is not necessarily "1" correctly. That is, the logic may erroneously become Sol K in the interval from To' to T1' due to noise superimposed on the waveform shown in FIG. 7(b). The error occurs stochastically depending on the magnitude of the noise and the amplitude at the signal point to be determined, but in order to minimize this error, it is necessary to The signal of KL2 may be determined at the center between ' and Tn+1', and the output logic obtained by determination at this timing may be held until the next determination timing.

Now, the influence of such band limitation and noise similarly appears at the output section of the low-pass filter 5 described above.

Therefore, here as well, KTn' and Tn+1
The method is taken to hold its output voltage in the middle between ' for only one clock period.

This is the role of the sample and hold circuit 8.

As described above, in order to determine the output of the low-pass filter 6 with constant timing and to sample and hold the output of the low-pass filter 5, it is necessary to regenerate the clock of the modulated signal on the receiving side. This is the role of the clock recovery circuit 13. The operation of this clock recovery circuit 13 is generally known and is not directly related to the detailed description of the present invention, so a description thereof will be omitted here.

The above-described decision feedback loop type two-phase phase modulation wave modulator is also explained in, for example, "1 Latest Digital Satellite Communication" (P114) published by the Japan Center for Technology and Economic Affairs.

[Problem that the invention seeks to solve]

In a decision feedback loop type demodulator that demodulates and reproduces a two-phase modulated wave as described above, a clock recovery circuit is usually indispensable in order to determine the decision time.

However, when such a demodulator is used in a communication system such as a time division multiplexing system in which input waves arrive in a burst form, there are the following problems.

First, the third section shows the aspect (frame format) of the received input signal, the timing of the selection signal input to the demodulator, and the selected positional relationship of the switch selected by this.
The diagram will be explained.

FIG. 3(1) shows an example of a frame structure used in a communication system called a time division multiplex system.

In this system, two-phase modulated waves from different transmitting stations arrive in bursts like A, B, C, and D at one frame period. In this case, the center frequency of each burst and the clock frequency of the modulation signal are approximately the same, but their phase relationships are independent. Therefore, in order to demodulate and reproduce these signals that arrive one after another using the decision feedback loop demodulator mentioned earlier, it is necessary to synchronize the phase with the carrier frequency (recovery of the reference carrier) and clock for each burst. (T 1 + T 1 in Fig. 7(a)
Obtain T, ', T, '... corresponding to... It is necessary to perform tarokku regeneration.

And, as is well known, these regenerations include
Since a predetermined time is required after the arrival of a burst, a modulation section for establishing synchronization, which is symmetrical to the preamble, is generally provided at the beginning of each burst. This part does not contribute to information transmission, and in order to improve transmission efficiency, it is better to keep it short.

Now, in a decision feedback loop type demodulator, the phase comparator 2.
Low pass filter 5. Sample and hold circuit 81 multiplier 9. It was explained earlier that the reference carrier is regenerated by the loop of the loop filter lO and the voltage controlled oscillator 11, but this operation is performed by sample-holding using the regenerated clock and multiplication by the correct regenerated signal determined at that time. It is assumed that

That is, in order to reproduce the reference carrier wave as accurately as possible, it is necessary to establish correct clock reproduction before that. For this reason, when using a decision feedback loop type demodulator, the length of the preamble must be longer than in other types of demodulators where carrier wave recovery and clock recovery are achieved independently. There was a problem that there was.

The present invention has been made to solve these problems, and an object of the present invention is to provide a two-phase phase modulation wave demodulator that can accurately reproduce burst data even if the preamble length is short.

[Means for solving problems]

The two-phase phase modulated wave demodulator according to the present invention includes first and second phase comparators and a clock recovery circuit to which branch signals from the input terminal of the two-phase phase modulated wave are input, and the first and second first and second low-pass filters that each output a low-frequency F wave from the output signal from the phase comparator; a sample-and-hold circuit that samples and holds the output signal of the first low-pass filter at the timing of the clock of the input wave;
a sign determination circuit that determines the output signal of the second low-pass filter at the timing of the clock; a multiplier that multiplies the output of the sample and hold circuit by the output of the sign determination circuit; A loop filter that waves, a voltage controlled oscillator whose oscillation frequency is controlled by the output voltage of this loop filter, and the phase of one signal obtained by branching the output of this voltage controlled oscillator into two are π/2 (r
ad) A two-phase phase modulated wave demodulator of a decision feedback loop type that reproduces a modulated signal from a two-phase phase modulated wave whose output terminal is the output of the sign determination circuit, which is not a phase shifter that shifts the phase; A third phase comparator connected to the regeneration circuit, a third low-pass filter that converts the output signal of the third phase comparator into a low-frequency F wave, and an output voltage of the third low-pass filter as a reference voltage. Compares the output according to the input voltage to logical%
A voltage comparator that outputs either logic 07 or logic 11, a first switch that selects the connection destination of the logic output of this voltage comparator using an external selection signal, and a logic signal connected by this first switch. a plurality of clock phase adjustment circuits that control the phase of their output signals as information; an oscillation source that provides an input signal source for the plurality of clock phase adjustment circuits; and an oscillation source that provides an input signal source for the plurality of clock phase adjustment circuits; a second switch selected by a selection signal from the clock phase adjustment circuit and a second switch connected to the sign determination circuit, the sample and hold circuit, and the third phase comparator; The clock phase of the output of the clock regeneration circuit that regenerates the clock is compared and controlled so that the two phases match, and the output of the clock phase adjustment circuit is selected for each corresponding burst, and this is applied to the sign determination circuit. and the sample timing of the sample and hold circuit.

Further, in the two-phase phase modulation wave demodulator according to another invention of the present invention, the output of the second low-pass filter and the output of the clock regeneration circuit are branched, and a second sign determination circuit is provided. The second sign determination circuit receives the branch signal of the low-pass filter of 'ig2 as input, uses the branch signal of the clock recovery circuit as a determination clock, and uses its output as the output signal of the present demodulator. be.

[Effect]

In this invention, an independent recovered clock source is prepared for each burst, and a pre-adjusted clock is selected and used each time each burst arrives.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a two-phase modulated wave demodulator according to the present invention.

In FIG. 1, the same reference numerals as in FIG.
16 is a voltage comparator that compares the output voltage of the low-pass filter 15 with a reference voltage and outputs either logic 077 or logic "1" according to the input voltage;
17 is a switch for selecting the connection destination of the logic output of this voltage comparator 16 by an external selection signal; 19t;
z...19n A clock phase adjustment circuit that uses the logic signal connected by this switch 17 as information to control the phase of its output signal, 18 is this clock phase adjustment circuit 1
9. 20 is a clock phase adjustment circuit 191-19. This is a switch that selects each of the outputs according to an external selection signal and connects it to the sign determination circuit 7, the sample hold circuit 8, and the phase comparator 14.

The phase comparator 14 is configured to compare the output signal of the clock recovery circuit 13 with the gold phase of the output signal of the switch 20 and output a voltage according to the result, and the oscillation source 18 is configured to The clock phase adjustment circuits 191 to 19n usually divide the frequency of this oscillation source 18 by M, and the phase of the output signal can be adjusted by the control signal from the switch 17. The switch 20 is configured to select a predetermined clock phase adjustment circuit at a predetermined time and connect it to the sign S determination circuit 7, sample hold circuit 8, and phase comparator 14 as described above.

21 is a control signal input terminal to which a control signal for controlling the switch 17 is supplied, and 22 is a control signal input terminal to which a control signal for controlling the switch 20 is supplied.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the output signal of the clock regeneration circuit 13 which regenerates the clock of the modulated signal from the modulated wave for each burst as explained in FIG. 6 above is input to the phase comparator 14. Further, the other input terminal of this phase comparator 14 is connected to a switch 2 which is supplied to the sign determination circuit 7 and the sample hold circuit 8.
The clock appearing at the output of 0 is input. Then, the phase comparator 14 compares the phases of both clocks and outputs a voltage according to the phase difference. This output signal is input to a voltage comparator 16 through a low-pass filter 15.

On the other hand, the low-pass filter 6 fluctuates the recovered clock output from the clock recovery circuit 13 due to the noise component included in the signal wave applied to the input terminal 1, and as a result, the phase comparator 3
This is to remove noise components that appear in the output.

Next, an example of the phase comparison characteristic of the phase comparator 14 will be described with reference to FIG. 4. In FIG. 4, the arrow indicates the phase difference (0 times - 02).

Now, the phase of the clock output from the clock regeneration circuit 13 is set to 01. The phase of the clock output from the switch 20 is θ! Then, the phase comparator 14 determines that θl≧θ1, that is, the phase of the clock output from the clock regeneration circuit 13 is equal to that of the switch 2.
If the phase of the clock output from the clock regeneration circuit 13 is ahead of the phase of the clock output from the switch 20, a positive voltage corresponding to the difference is output. If the phase of the clock is delayed, a negative voltage corresponding to the difference is output.

As a result, the output of the voltage comparator 16 is the former, that is,
When θ1≧02, −E(V) is output, and when the latter, that is, θ■<θ2, −E(b) is output. The output of this voltage comparator 16 is then passed through a switch 17 to a clock phase adjustment circuit 19. ~19n is input to each phase difference information input terminal.

Now, this switch 17 is controlled by a control signal inputted to the control signal input terminal 21, and selects which clock phase adjustment circuit the output of the voltage comparator 16 is inputted to for a predetermined period.

FIG. 3(b) shows the timing of the selection signal applied to the control signal input terminal 21 and the switch 1 selected thereby.
7 shows the relationship between the positions. The model axis in FIG. 3(b) is a time axis, which coincides with the time axis in FIG. 3(-).

That is, near the trailing edge of each burst, the position of switch 17 is selected to be in the numbered position shown above each signal.

Now, in the above description of the conventional example, it was mentioned that it takes a predetermined time for the clock regeneration circuit 13 to correctly regenerate the clock of the modulated wave after receiving the received wave of each burst.

The role of the switch 17 is to allow the clock regeneration circuit 13 to regenerate a correct clock and to input phase comparison information written as a result to each clock phase adjustment circuit 191 to 19tt.

FIG. 3 shows a case where the number of bursts in one frame is four. In this case, the switch 17 is selected from four positions: 1, 2, and 3.4. In addition, the clock phase adjustment circuits 19, . 19. ...19n
There are 4 pieces. When the number of bursts in one frame is N, the positions of the switch 17 are 1 to Nt, and the clock phase adjustment circuits are provided in positions 191 to 19n, respectively.

Next, the operations of the oscillation source 18 and the clock phase adjustment circuit 191 will be explained.

FIG. 5 shows an example of the internal configuration of the clock phase adjustment circuit. In FIG. 5, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted. Clock phase adjustment circuit 191
is a logic circuit, an up/down counter, and a frequency divider M-
It is composed of 1/M/M+1. 23 is a terminal connected to the input terminal of the switch 20 shown in FIG.
4.25 is a terminal.

Now, if the output frequency of the oscillation source 18 is frn, and the frequency division number of the frequency divider M-1/M/M+1 is M, then the output frequency fc is fc==f/M. Here, the output frequency f1n of the oscillation source 18 is set by the oscillation source 18 with high precision so that the output frequency fe of the frequency divider matches the modulation frequency of each burst.

Now, the positive pulse shown in FIG. 3(b) is applied to the control signal input terminal 21 shown in FIG. shall be. Then, the positive pulse (logic 11#) is applied to the terminal 24 (logic 11#) of the clock phase adjustment circuit 191 (
(see FIG. 5), and the logic output of the voltage comparator 16 is input to the clock phase adjustment circuit 19 through the switch 17.
1 (see FIG. 5).

At this time, if the logic of the signal applied to the terminal 25 is 111, the countdown terminal of the up/down counter (
If the logic 11" appears on the terminal 25 (DOWN) and the logic of the signal applied to the terminal 25 is 'O", the logic %1N appears on the count up terminal (up). and,
Since a positive logic pulse is input once to the terminal 24 at a predetermined timing every time the pulse A shown in FIG.

This up/down counter operates to count up or count down according to this pulse, and when a difference of more than a predetermined value occurs between the number of up and down counts, the CARRY (C) signal or B
The ORROW (B) signal is generated, and at the same time, the counter is reset (RT) and the count up/down operation continues again. On the other hand, the frequency dividers M-1/M/M+1 normally operate as M frequency dividers. When the B signal is input from the up/down counter, M-1 frequency division is performed for one division period, and when the C signal is input, M+1 frequency division is performed for one division period. That is,
゛ 2π □ (rad) by one B signal or one C signal
The clock phase of the output terminal 23 is controlled to be advanced or delayed by the amount of time.

The above is the operation of the oscillation source 18 and the clock phase adjustment circuit 191. In addition, the clock phase adjustment circuit 19°...19
The operation is the same for m.

Next, the output signals of the clock phase adjustment circuits 191 to 19n are inputted to the sign determination circuit 7 and the sample hold circuit 8 through the switch 20, respectively.

The position of this switch 20 is controlled by a signal applied to a control signal input terminal 21, as shown in FIG. 3(c). Here, the number 1.2 in Figure 3(c)...
- 4 indicates the position of the switch 20.

That is, when a burst of 1 arrives, the output of the clock phase adjustment circuit 191 is output, and when a burst of 2 arrives, the output of the clock phase adjustment circuit 19! The clock signal sources of the sign determination circuit 7 and the sample-and-hold circuit 8 are selected such that the output of .

And this clock phase v! 4 adjustment circuits 191-191
When the corresponding burst arrives, each output is connected to the sign determination circuit 7 and the sample hold circuit 8, and its branch signal is input to the phase comparator 14, and its phase is compared with the clock of the clock recovery circuit 13. be done. and,
As described above, the output phase is controlled by the phase comparison information of the timing at which the clock regeneration circuit 13 correctly regenerates the burst clock.

- In general, the rate of change of the clock of each input signal is very slow, and the frequency difference between each burst is also very small. Therefore, if the frequency stability of the oscillation source 180 is sufficiently increased and phase correction information is given once for each burst, the output signals of the clock phase adjustment circuits 191 to 19n will be
It can always be sufficiently controlled to match that of each burst.

The size of the count until the C signal and B signal of the up/down counter in Figure 5 are output plays the role of a kind of low-pass filter, and this depends on the size of the input noise, the burst repetition period, and the modulation waveform. It is designed to an appropriate value depending on the magnitude of fluctuation in the clock frequency.

Note that the control signal group applied to the control signal input terminals 21 and 22 in FIG. Given.

Note that in the above embodiment, the output of the sign determination circuit 7 is used as the output terminal, but the output of the low-pass filter 6 and the output of the clock recovery circuit 13 are branched, and a second sign determination circuit is provided. The output of the determination circuit can also be used as an output terminal.

That is, as a modification of FIG. 1, the structure shown in FIG. 2 may be used.

In FIG. 2 showing another embodiment of the invention, the same reference numerals as in FIG. 1 indicate corresponding parts, and 26 is a sign determination circuit 7.
27 is the output terminal of this sign determination circuit 26.

In the embodiment shown in FIG. 2, the output of the low-pass filter 6 and the output of the clock recovery circuit 13 are branched, and a sign determination circuit 26 is provided. The branch signal of the clock regeneration circuit 13 is used as the clock for determination, and the output of the sign determination circuit 26 is used as the output signal of the present demodulator.

The part consisting of the input terminal 1 to the clock regeneration circuit 13 shown in FIG. 1 regenerates the carrier wave of the received signal, obtains a demodulated wave at the output of the low-pass filter 6, and determines the demodulated wave at the optimal timing. It plays two functions: regenerating the modulated signal and outputting it to the output terminal 12.

Incidentally, the allowable range of the phase accuracy of the reproduced clock to achieve the former effect may be relatively large. In such a case, the embodiment shown in FIG. 2 is effective.

By configuring as shown in FIG. 2, the phase control accuracy of the clock phase adjustment circuits 191 to 19n can be made lower than in the embodiment shown in FIG.
As a result, the design conditions for the clock recovery circuit for each burst, which is comprised of the phase comparator 14 or the control signal input terminal 22, can be relaxed.

On the other hand, reproduction of the modulated signal is determined by the added sign determination circuit 26 at accurate timing based on the clock from the clock reproduction circuit 13, and an accurate reproduction signal can be obtained at the output terminal 27.

〔Effect of the invention〕

As explained above, according to the present invention, each dedicated clock phase adjustment circuit is provided corresponding to each burst of input,
The phases of these outputs are compared with the output after the clock regeneration circuit accurately regenerates the clock of the burst, and the information is used to correct the phase of the output signal of each of the clock phase adjustment circuits. Since these are selected and used for each corresponding burst, the clock for each burst is always prepared in the demodulator, and an accurate lock is given to the beginning of any burst. . Therefore, unlike conventional methods, it is not necessary to go through the process of first performing clock recovery and then carrier wave recovery for each burst. This has the effect that burst data can be reproduced accurately even if the burst is short.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a two-phase phase modulated wave demodulator according to the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. An explanatory diagram showing the aspect of the input signal (frame format), the timing of the selection signal input to the demodulator, and the selection position relationship of the switches selected by this, and Fig. 4 shows the phase detection characteristics of the phase comparator used in the present invention. FIG. 5 is a circuit diagram showing an example of the internal configuration of a clock phase adjustment circuit used in the present invention; FIG. 6 is a block diagram showing an example of a conventional two-phase modulated wave demodulator; FIG. The figure is an explanatory diagram showing a logical example of a modulated signal and an example of a demodulated output waveform corresponding thereto. 1...Input terminal, 2.3...Phase comparator, 4...
・Life・Phase shifter, 516...11@Low pass filter, 7
... Sign determination circuit, 8 ... Sample hold circuit, 9 ... Multiplier, 10 ... #- ... Loop filter,
11... Voltage controlled oscillator, 12... Output terminal,
13...Clock regeneration circuit, 14...Phase comparator, 15...Cloudy low-pass filter, 16...Tt
Pressure comparator, 17@... switch, 18, fist-- oscillation source, 191-19n... clock phase adjustment circuit, 20
...Switch, 26...Sign determination circuit.

Claims (2)

[Claims] (1) First and second phase comparators and clock recovery circuits to which branch signals from the input terminals of two-phase phase modulated waves are input, and output signals from the first and second phase comparators, respectively. first and second low-pass filters that perform low-pass filtering; a sample-hold circuit that samples and holds the output signal of the first low-pass filter at the timing of the clock of the input wave; and a sample-hold circuit that samples and holds the output signal of the second low-pass filter. a sign determination circuit that makes a determination based on the timing of the clock; a multiplier that multiplies the output of the sample and hold circuit by the output of the sign determination circuit; a loop filter that filters the output signal of the multiplier; It consists of a voltage controlled oscillator whose oscillation frequency is controlled by an output voltage, and a phase shifter which shifts the phase of one of the two signals obtained by branching the output of this voltage controlled oscillator by π/2 (rad),
A third phase comparator connected to the clock regeneration circuit in a decision feedback loop type two-phase modulated wave demodulator that reproduces a modulated signal from a two-phase phase modulated wave whose output terminal is the output of the code determination circuit. and a third low-pass filter that performs low-pass filtering on the output signal of this third phase comparator, and compares the output voltage of this third low-pass filter with a reference voltage, and outputs logic "0" according to the input voltage. a voltage comparator that outputs a logic "1"; a first switch that selects the connection destination of the logic output of this voltage comparator using an external selection signal; a plurality of clock phase adjustment circuits that control the phase of their output signals using the logical signals obtained as information; an oscillation source that provides an input signal source for the plurality of clock phase adjustment circuits; and a plurality of clock phase adjustment circuits. a second switch that selects each output of the clock phase adjustment circuit according to an external selection signal and connects the sign determination circuit, the sample hold circuit, and the third phase comparator, and the clock phase of the output of the clock regeneration circuit that regenerates the clock of the burst for each burst, and controls the two so that their phases match, and selects the output of the clock phase adjustment circuit for each corresponding burst. 2, characterized in that this is set as the determination timing of the sign determination circuit and the sample timing of the sample hold circuit.
Phase modulation wave demodulator. (2) first and second phase comparators and clock regeneration circuits to which branch signals from the input terminals of the two-phase phase modulated wave are input, and output signals from the first and second phase comparators, respectively; first and second low-pass filters that perform low-pass filtering; a sample-hold circuit that samples and holds the output signal of the first low-pass filter at the timing of the clock of the input wave; and a sample-hold circuit that samples and holds the output signal of the second low-pass filter. a first sign determination circuit that determines based on the timing of the clock; a multiplier that multiplies the output of the sample and hold circuit by the output of the first sign determination circuit; and a loop filter that filters the output signal of the multiplier. , a voltage controlled oscillator whose oscillation frequency is controlled by the output voltage of this loop filter, and a phase shifter that shifts the phase of one of the signals obtained by branching the output of this voltage controlled oscillator by π/2 (rad). In a decision feedback loop type two-phase phase modulated wave demodulator that reproduces a modulated signal from the two-phase phase modulated wave,
a third phase comparator connected to the clock recovery circuit; and a third phase comparator for low-pass filtering the output signal of the third phase comparator.
a low-pass filter, a voltage comparator that compares the output voltage of this third low-pass filter with a reference voltage and outputs logic "0" or logic "1" according to the input voltage, and the logic of this voltage comparator. A first switch that selects the output connection destination using an external selection signal, and a plurality of clock phases that control the phase of the output signal using the logic signal connected by the first switch as information. an adjustment circuit, an oscillation source that provides an input signal source for the plurality of clock phase adjustment circuits, and each output of the plurality of clock phase adjustment circuits are selected by an external selection signal, and the first sign determination is performed. and a second switch connected to a sample and hold circuit and a third phase comparator, the output of the clock regeneration circuit regenerating the phase of the output signal of the clock phase adjustment circuit and the clock of the burst for each burst. The output of the clock phase adjustment circuit is selected for each corresponding burst, and this is used as the judgment timing of the first sign judgment circuit and the sample hold. The circuit is configured to have a sample timing, and the output of the second low-pass filter and the output of the clock recovery circuit are branched, and a second sign determination circuit is provided, and this second sign determination circuit is connected to the second sign determination circuit. 2-phase phase modulation characterized in that the branch signal of the low-pass filter is input, the branch signal of the clock recovery circuit is used as a judgment clock, and its output is used as the output signal of the demodulator. wave demodulator.