JPS6348917A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To reduce the impedance in the inside of a latch circuit and to reduce the leaked signal to the output side by constituting a converter comprising a 1st pair transistors (TRs) sending an output signal independently corresponding to the input and a latch circuit comprising the 2nd pair TRs receiving each output signal. CONSTITUTION:The D/A converter consists of a positive input terminal 1, a negative input terminal 2, a positive clock input terminal 3, a negative clock terminal 4, a positive output terminal 5, a negative output terminal 6, a high potential power terminal 7, a low potential power terminal 8, TRs 20a-20f, and resistors 21a, 21b, and constant current sources 22a, 22b giving a bias current independently of the input signal are provided newly and they are connected to the emitter of the TRs 20a, 20b. Thus, the impedance at a connecting point (a) among the TRs 20a, 20c and the TR 20b and the constant current source 22a, and a connecting point between the TRs 20e, 20f is lowered and spike noise is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital-to-analog converter used especially when high speed and high precision are required.

[Conventional technology]

Traditionally, digital-to-analog converters made for high-speed applications produce glyphs due to the time lag between multiple digital input signals. A launch circuit was added to the digital input stage to prevent glitches from occurring by adding a launch circuit to the digital input stage, in which the switch consisting of a transistor was operated by a common lock signal.

[Problem that the invention seeks to solve]

However, such conventional devices have a problem in that changes in the rising or falling edge of the clock appear as spike noise in the output due to parasitic effects such as parasitic capacitance of the transistor.

Although this spike noise is attenuated by the circuit connected to the launch circuit, it is propagated to the output side and contributes to output noise. FIG. 5 shows a simulation circuit for simulating this performance, and FIG. 6 shows the frequency characteristics from the input to the output of the circuit. Since the spike noise generated in the latch circuit has an amplitude of o and about 1 vpp, for example, a component of 1 GIlz will be attenuated by about 60 dBK and transmitted to the output. That is, full scale 1
If we assume a digital-to-analog converter of vl) l), -80 dB of noise will appear in the output. This is a value for one switch, and in actual cases, the upper switch is configured using a segment method, so it is composed of many switches, and in the normal case, there are 8 to 16 switches. becomes.

Therefore, the noise generated in the output will be superimposed by the number of switches, so for example, in the case of 8 switches, minus 60
This will generate a certain amount of noise.

In other words, due to the spike noise generated in the launch circuit, a digital-to-analog converter that achieves the same speed settling characteristics that requires consideration of the IG)I component can only obtain an S/N of 60 dB (10-bit accuracy). The problem is that I can't.

This is because the higher the speed, the greater the transfer gain of the spike noise generated in the latch circuit to the output, and the greater the spike noise generated in the launch circuit, resulting in higher precision. This has the problem of hindering the development of

[Means for solving problems]

In order to solve this problem, the present invention provides a current bypass circuit inside the launch circuit.

[Effect]

By flowing a current through the current bypass circuit, the impedance inside the latch circuit is reduced, and the amount of signal leaking to the output side is reduced.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, 1 is a positive input terminal, 2 is a negative input terminal, 3 is a positive clock input terminal, 4 is a negative clock input terminal, 5 is a positive output terminal, 6 is a negative output terminal, and 7 is a high-level 8 is a low power supply terminal, 20a to 20f are transistors, 21a and 21b are resistors, and 223 to 22c are constant current sources.

A feature of this circuit is that it is provided with constant current sources 22a and 22b that flow bias currents regardless of the clock input signal. When this constant current source is not present, for example, when the clock input terminal 3 is at the "1" level and the clock input terminal 4 is at the "0" level, no current flows through the transistors 20d to 20f, and the transistors 20d to 20f are in an off state, and the symbol is The impedance (resistance) between the connection point shown and ground increases. Therefore, the high frequency component of the clock signal supplied to the clock input terminal 4 is connected to the base-collector capacitance of the transistor 20f.
Since the voltage is divided by the impedance of the connection point shown in the symbol, high-potential high-frequency components leak into the output terminal, causing spike noise.

Further, even when the signal phases of the clock input terminals 3.4 are reversed, the connection point a has a high impedance, and similarly large spike noise is generated. However, the constant current source 22
By providing a and 22b, the impedance at the connection point between symbol a and symbol A is reduced, so that the leakage voltage that conventionally occurs due to voltage division is reduced.

FIG. 2 is a circuit diagram showing an embodiment of an n-bit digital-to-analog converter constructed to which the present invention is applied.
2) The bits are weighted by a ladder. In the figure, 9 is a switch, 10 is a current source, 11 is a switch driver, 12 is a latch circuit, 13 is a digital input terminal, 14 is an output terminal, 15 is a clock input terminal,
16 is a decoder, and 17 is a ladder. FIG. 3 shows a specific example of a launch circuit, in which the constant current sources 22a, 22 of FIG.
b as transistors 20g, 20h and resistors 21c, 21d
It is composed by:

Figure 4 (a) shows the output waveforms of the positive output terminal 5 and negative output terminal 6 when the constant current source current 1b and Is are used as parameters, and Figure 4 (b) shows the clock signal. FIG. In this figure, current 1b of constant current source =
O is the characteristic in the conventional circuit, Ib=0.5 m
When A, it can be seen that the spike noise is less than half of the value generated by the conventional circuit. Therefore, accuracy can be improved by about 6 dB compared to the conventional configuration.

〔Effect of the invention〕

As explained above, this invention adds a current bypass circuit to the latch circuit to lower the impedance, thereby reducing spike noise, which has the effect of making it possible to configure a highly accurate digital-to-analog converter. has.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an embodiment of a digital-to-analog converter constructed by applying the invention, and Fig. 3 is a latch diagram in Fig. 2. 4 is a graph showing the characteristics of the circuit shown in FIG. 3, FIG. 5 is a circuit diagram showing a circuit for simulating the characteristics of a conventional circuit, and FIG. 6 is a circuit diagram showing an example of the circuit. It is a graph showing the simulation results. ■...Positive input terminal, 2...Negative input terminal, 3
...Positive clock input terminal, 4...Negative clock input terminal, 5...Positive output terminal, 6...Negative output terminal, 7...High-level power supply terminal , 8...Low power supply terminal, 9...Switch, 20a-20f...
...Transistor, 21a to 21e---=Resistance, 2
2a to 22C...constant current source. Patent applicant Nippon Telegraph and Telephone Corporation Agent Yamakawa administration (and one other person) Figure 3 Figure 4 Figure 5 Figure 6 f (GHz)

Claims (1)

[Claims] A first pair of transistors having a common emitter, a positive input signal being supplied to one base, a negative input signal being supplied to the other base, and output signals corresponding to each input being sent out independently; In a digital-to-analog converter equipped with a latch circuit consisting of a second pair of transistors in which the output signals of each of the first pair of transistors are independently supplied to the base, the emitters of the first and second pair of transistors are independently supplied. A digital-to-analog converter characterized by adding a current bypass circuit to the converter.