JPS6349936B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase lock loop circuit designed to reduce power consumption.

In recent years, wireless communication equipment, etc., have become more and more popular due to circuit simplification and SN
In order to improve the ratio, frequency synthesizers and modulation/demodulation circuits using phase lock loop circuits (PLL circuits) are often used. FIG. 1 is a circuit block diagram showing the basic configuration of a frequency synthesizer using a conventional phase lock loop circuit. This frequency synthesizer uses a phase comparator 4 to detect the phase difference between the output of a reference oscillator 1 and the output obtained by dividing the output of a voltage controlled oscillator 2 by a frequency divider 3.
This detection output is supplied to the voltage controlled oscillator 2 via the loop filter 5 to obtain a desired oscillation frequency.

However, in devices using such conventional phase lock loop circuits, since the phase lock loop circuit is always in an operating state, the power consumption of the phase lock loop circuit itself is large, and the power consumption of the phase lock loop circuit itself is large. It was difficult to apply it to low power consumption equipment.

The present invention has been made focusing on the above circumstances,
The purpose is to provide a phase lock loop circuit that operates efficiently and intermittently to reduce power consumption, and that can be applied particularly to low power consumption equipment. It is in.

An embodiment of the present invention will be described below with reference to FIG. In this figure, the same parts as in FIG. 1 are given the same reference numerals and detailed explanations will be omitted. In FIG. 2, a first switch 6 is interposed between the loop filter 5 and the voltage controlled oscillator 2, and each circuit except the voltage controlled oscillator 2, that is, the reference oscillator 1, the frequency divider 3, , a second switch 7 is provided in the power supply path to the phase comparator 4 and the loop filter 5. These first and second switches 6 and 7 are controlled to open and close by a switch control circuit 8. On the other hand, the voltage controlled oscillator 2 and the first
A memory circuit 9 is provided in parallel to the voltage controlled oscillator 2 between the switch 6 and the voltage controlled oscillator 2. This memory circuit 9
is an analog-to-digital converter (A/D converter)
91, a memory 92, and a digital-to-analog converter (D/A converter) 93. Immediately before the switches 6 and 7 are opened, the control voltage of the voltage controlled oscillator 2 is converted into a digital value by the A/D converter 91. The digital value of the control voltage stored in the memory 92 is read out during the opening period of the switches 6 and 7 and converted into an analog value by the D/A converter 93, and then converted to an analog value by the D/A converter 93. 2. Incidentally, V indicates an input terminal of a power supply output.

With this configuration, the switch control circuit 8
outputs a switch closing signal from the first and second
When the switches 6 and 7 are closed, the phase lock loop circuit main body starts locking operation, and the oscillation frequency of the voltage controlled oscillator 2 is determined by the output frequency of the reference oscillator 1 and the frequency division number of the frequency divider 3. Lock to value. Then, when the lock operation is completed and, for example, a lock completion signal is output from the phase comparator 4 and the switch control circuit 8 outputs a switch open signal, the control voltage at this time is converted into a digital signal by the A/D converter 91. The value is converted into a value and stored in the memory 92, and then the first and second switches 6 and 7 are opened to open the loop of the phase lock loop circuit, and to each circuit except the voltage controlled oscillator 2. The power supply is cut off and each circuit becomes inoperable. In other words, the phase lock loop circuit main body is in a state where no power consumption occurs except for the voltage controlled oscillator 2. However, during this loop opening period, the digital value of the control voltage stored in the memory 92 is read out, converted into an analog value by the D/A converter 93, and then supplied to the voltage controlled oscillator 2. Therefore, the voltage controlled oscillator 2 continues to output the same oscillation frequency as during lock operation.

For example, when the switch control circuit 8 outputs a switch close signal after a predetermined period of time has elapsed as counted by the counter of the switch control circuit 8, the first and second switches 6 and 7 are closed, and the phase lock loop circuit is closed. The main unit performs the locking operation again,
After the lock is completed, the control voltage value stored in the memory 92 is rewritten to the new control voltage value at the time the lock is completed. Therefore, if the oscillation frequency of the voltage controlled oscillator 2 fluctuates during the loop opening period, the oscillation frequency of the voltage controlled oscillator 2 is corrected by rewriting the control voltage value.

Similarly, every time the switch control circuit 8 outputs a switch closing signal, the phase lock loop circuit main body performs a lock operation, and the memory 92
The control voltage stored in is rewritten. That is, the phase lock loop circuit main body performs an intermittent lock operation.

In this way, the first switch 6 is provided in the loop of the phase lock loop circuit main body of this embodiment, and the second switch 7 is provided in the power output supply path to each circuit except the voltage controlled oscillator 2, and switch control is performed. circuit 8
Since the opening and closing of the phase lock loop circuit is controlled by Therefore, intermittent lock operation can be performed, and as a result, power consumption can be significantly reduced. In particular, in this embodiment, the power to the frequency divider 3, which consumes a large amount of power, is turned off, so the effect is extremely large.

Furthermore, in this embodiment, the power supply is cut off and the loop is opened in synchronization with the lock completion signal output from the phase comparator 4.
It is possible to immediately cut off the power supply as soon as possible after the lock operation of the PLL is completed, for example, when the time required to store the control voltage in the memory 92 has elapsed, and as a result, the loop remains in the locked state. Since the circuit does not continue to operate unnecessarily, the power consumption of the circuit can be reduced accordingly. Further, in this case, since the accurate control voltage after the completion of locking the loop is stored in the memory 92, accurate oscillation operation can be performed during the loop opening period. In other words, with the present invention, the PLL without the voltage controlled oscillator can be
Power consumption by the circuit can be reduced most efficiently.

Therefore, if the phase lock loop circuit of the present invention is used in a frequency synthesizer or a modulation/demodulation circuit, it is possible to realize a radio device with extremely low power consumption, and as a result, it is possible to realize a radio device with extremely low power consumption. Application is also possible.

In addition, since the control voltage is stored in the storage circuit 9 consisting of the A/D converter 91, memory 92, and D/A converter 93, the control voltage is more protected from leaks than when using a capacitor, for example. It can be stably maintained without being affected, and as a result, the power supply voltage supply interruption period can be set for a long time, thereby further reducing power consumption. In addition, the A/D converter 91 and the memory 92
By using the storage circuit consisting of the D/A converter 93 and the D/A converter 93, the control voltage can be stored in an extremely short time compared to a capacitor after the loop is locked. Therefore, the loop can be returned to the open state as soon as possible after the lock is completed, thereby shortening the loop closing period and further increasing the effect of reducing power consumption.

Note that the present invention is not limited to the above embodiments. For example, a capacitor may be used as the means for storing the control voltage. Furthermore, in the above embodiment, the power supply to all the circuits except the voltage controlled oscillator 2 is cut off, but it is also possible to cut off the power supply to only the frequency divider, which consumes a large amount of power. Just cut off the supply.
In addition, the types and configurations of the first switch and the second switch, the configuration of the phase lock loop circuit body, etc. may be modified in various ways without departing from the gist of the present invention.

As detailed above, the present invention provides first and second switches for respectively opening and closing the loop of the phase lock loop circuit body and the power supply paths to each circuit, and also provides a control circuit for these switches. This switch control circuit detects the completion of locking of the phase lock loop circuit main body when the loop is closed, and opens the first and second switches respectively in synchronization with this detection timing, and also opens the first switch. The first and second switches are respectively closed after a predetermined period of time has elapsed since then, and a memory circuit is provided at the control voltage input terminal of the voltage controlled oscillator. The control voltage of the voltage controlled oscillator when the lock of the phase lock loop circuit main body is completed is stored, and the stored control voltage is supplied to the voltage controlled oscillator during the opening period of the first switch to continue the oscillation operation. It is something.

Therefore, according to the present invention, the phase lock loop circuit main body can be stably operated intermittently over a long period, and the lock operation period in this intermittent operation can be set short, thereby significantly reducing power consumption. A phase lock loop circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing the basic configuration of a frequency synthesizer using a conventional phase-lock loop circuit, and FIG. 2 is a circuit block diagram of a frequency synthesizer using a phase-lock loop circuit according to an embodiment of the present invention. It is. 1... Reference oscillator, 2... Voltage controlled oscillator (VCO), 3... Frequency divider, 4... Phase comparator, 5
...Loop filter, 6...First switch, 7
...Second switch, 8...Switch control circuit,
9...Memory circuit, 91...A/D converter, 92...
...Memory, 93...D/A converter.

Claims (1)

[Claims] 1 A phase lock loop circuit body and a first phase lock loop circuit that opens and closes the loop of this phase lock loop circuit body.
a second switch for opening/closing a power supply path to at least one of the circuits constituting the phase lock loop circuit body except for the voltage controlled oscillator; and the first switch Each time the phase lock loop circuit is closed, completion of locking of the phase lock loop circuit body is detected, and in synchronization with this detection timing, the first and second switches are respectively opened, and a predetermined period of time elapses from the opening of the first switch. a switch control circuit that closes the first and second switches after a lapse of time, and a control voltage of the voltage controlled oscillator in a state in which the lock of the phase lock loop circuit main body is completed when the first switch is closed. A phase lock loop circuit comprising: a storage circuit that supplies the stored control voltage to the voltage controlled oscillator during the open period of the first switch to continue the oscillation operation.