JPS6350094A - Manufacture of multilayer circuit board - Google Patents
Manufacture of multilayer circuit boardInfo
- Publication number
- JPS6350094A JPS6350094A JP19416786A JP19416786A JPS6350094A JP S6350094 A JPS6350094 A JP S6350094A JP 19416786 A JP19416786 A JP 19416786A JP 19416786 A JP19416786 A JP 19416786A JP S6350094 A JPS6350094 A JP S6350094A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- layer
- board
- multilayer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000010410 layer Substances 0.000 claims description 47
- 239000000919 ceramic Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 229920001721 polyimide Polymers 0.000 claims description 9
- 239000009719 polyimide resin Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 15
- 229910052737 gold Inorganic materials 0.000 description 15
- 239000010931 gold Substances 0.000 description 15
- 238000007747 plating Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920006332 epoxy adhesive Polymers 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明ｌよ、コンピュータ等の電子機器に使用するのに
適する多層回路基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a multilayer circuit board suitable for use in electronic equipment such as computers.
従来この種の多層回路基板には、装置の処理能力の高速
化を達成するため、配線の高速化と高密度−化にないす
る努力がなされて来た。具体的には、高速化については
、誘電率の低い有機樹脂などを絶縁材に使用したり、銅
などの低抵抗の導電材を使用し、高密度化については、
配線パターンの微細化、もしくは、配線層の高多層化を
進めて来た。Conventionally, in this type of multilayer circuit board, efforts have been made to increase the speed and density of wiring in order to increase the processing capacity of the device. Specifically, to increase speed, we use organic resins with a low dielectric constant as insulating materials, and use low-resistance conductive materials such as copper, and to increase density,
Progress has been made in miniaturizing wiring patterns or increasing the number of wiring layers.
（例えば、日経エレクトロニクス１９８４年８月２７日
号Ｐ１４５〜Ｐ１５９、日経エレクトロニクス１９８５
年６月１７日号Ｐ２４３〜Ｐ２６６）〔解決すべき問題
点〕
上記従来の多層回路基板における配線パターンの微細化
には、配線の断面積が小さくなるため、導体抵抗が高く
なり配線の高速化を阻害すると言う欠点があった。また
、配線層の高多層化には、全層をセラミック・グリーン
シートと厚膜印刷配線の同時焼成で行う方法があるが、
セラミックの比誘電率が低くないために配線の高速化に
は不適当である。一方、有機樹脂を層間絶縁に用いて高
多層配線を形成した場合には、セラミック基板上に、配
線層を下層より順次形成して行かねばならず、製造日数
が多（なり、設計変更に対する迅速な対応ができない事
と、製造コストが高くなると言う欠点があった。(For example, Nikkei Electronics August 27, 1984 issue P145-P159, Nikkei Electronics 1985 issue
(June 17, issue P243-P266) [Problems to be solved] The miniaturization of the wiring patterns in the conventional multilayer circuit board mentioned above reduces the cross-sectional area of the wiring, which increases the conductor resistance and increases the speed of wiring. It had the disadvantage of inhibiting the In addition, to increase the number of wiring layers, there is a method in which all layers are fired simultaneously with ceramic green sheets and thick film printed wiring.
Since the dielectric constant of ceramic is not low, it is unsuitable for high-speed wiring. On the other hand, when organic resin is used for interlayer insulation to form highly multilayer wiring, the wiring layers must be formed sequentially from the bottom layer on the ceramic substrate, which increases the number of manufacturing days (resulting in rapid response to design changes). The disadvantages were that it was not possible to respond in a timely manner and that the manufacturing cost was high.
本発明は、上記従来の問題点に着目してなされたもので
、積層に要する日数を短縮でき、かつ製造欠陥に起因す
る損失工数を低減できる多層回路基板の製造方法を提供
せんとするものである。The present invention has been made in view of the above-mentioned conventional problems, and aims to provide a method for manufacturing a multilayer circuit board that can shorten the number of days required for lamination and reduce man-hours lost due to manufacturing defects. be.
そのために、本発明は、ポリイミド系樹脂を層間絶縁と
して、セラミック基板上に複数の配線層を形成すること
により構成される多層回路基板の製造方法において、あ
らかじめ多層回路基板を下層部を構成する第１の配線基
板と、上層部を構成する第２の配線基板とにわけ、セラ
ミック基板上に下層より順次配線層を積層して第１の配
線基板を形成する第１の工程と、アルミニウム等の金属
板上に下層より順次もしくは上層より順次配線層を積層
して第２の配線基板を形成する第２の工程と、第２の配
線基板の金属板を希塩酸により溶解除去する第３の工程
と、第１の配線基板の表面に形成された金属パッドと、
第２の配線基板の表面に形成された金属パッドとを半田
付けもしくは導電性接着剤で接着する第４の工程とを有
することを特徴とする多層回路基板の製造方法を提供す
るものである。To this end, the present invention provides a method for manufacturing a multilayer circuit board formed by forming a plurality of wiring layers on a ceramic substrate using polyimide resin as interlayer insulation. A first step is to form a first wiring board by laminating wiring layers sequentially from the bottom layer on a ceramic substrate, and a second wiring board constituting an upper layer. a second step of laminating wiring layers on the metal plate sequentially from the bottom layer or from the top layer to form a second wiring board; and a third step of dissolving and removing the metal plate of the second wiring board with dilute hydrochloric acid. , a metal pad formed on the surface of the first wiring board;
The present invention provides a method for manufacturing a multilayer circuit board, comprising a fourth step of bonding the second wiring board to a metal pad formed on the surface thereof by soldering or using a conductive adhesive.
以下、本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図は、本発明の第一の実施例を示す縦断面図である
。この実施例では、多層回路基板をセラミック積層配線
基板１を有する下層部用の第１の配線基板１０と、金属
板としてのアルミニウム板３０を有する上層部用の第２
の配線基板４０とに 。FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention. In this embodiment, the multilayer circuit board is comprised of a first wiring board 10 for the lower layer having a ceramic laminated wiring board 1, and a second wiring board 10 for the upper layer having an aluminum plate 30 as a metal plate.
to the wiring board 40.
あらかじめわけている。セラミック積層配線基板１は、
−辺１５センチメートルの正方形で、厚さは、３ミリメ
ートルである。このセラミック積層配線基板は、酸化ア
ルミニウムを主成分とする層間絶縁層１１と、４種の、
タングステンを用いて形成された電源配線層１２，１３
，１４，１５とが交互に積層されている。また、乙のセ
ラミック積層配線基板１には、表裏を貫通し、あるいは
、各電源配線層と基板表面に形成された金パツド１６゜
１７とを接続するための、スルーホール配線２０が形成
されている。スルーホール配線は、タングステン、もし
くはモリブデンで形成されている。It is divided in advance. The ceramic laminated wiring board 1 is
- It is a square with sides of 15 cm and a thickness of 3 mm. This ceramic laminated wiring board includes an interlayer insulating layer 11 mainly composed of aluminum oxide, and four types of
Power wiring layers 12 and 13 formed using tungsten
, 14, and 15 are alternately stacked. In addition, through-hole wiring 20 is formed in the ceramic laminated wiring board 1 for penetrating the front and back sides or for connecting each power supply wiring layer to the gold pads 16 and 17 formed on the surface of the board. There is. The through-hole wiring is made of tungsten or molybdenum.
このセラミック積層配線基板は、第１の工程に先立って
、あらかじめ準備されているものである。This ceramic laminated wiring board is prepared in advance prior to the first step.
第１の工程では、基板１の表面に電源配線１８を金めつ
きで形成し、これを覆う第１のポリイミド樹脂絶縁層１
．９を形成し、その上に第１の信号配線２１を金めつき
で形成し、続いて第２のポリイミド樹脂絶縁層２２をそ
の上に形成し、さらに第２の信号配線２３を金めつきで
形成し、続いて第３のポリイミド樹脂絶縁層２４を形成
する。最後に、金パツド２５と電源配線２６とを金めつ
きで形成して第１の配線基板１０を得る。In the first step, a power supply wiring 18 is formed on the surface of the substrate 1 by gold plating, and a first polyimide resin insulating layer 1 is formed to cover this.
．． 9, a first signal wiring 21 is formed thereon by gold plating, a second polyimide resin insulating layer 22 is formed thereon, and a second signal wiring 23 is formed by gold plating. Then, a third polyimide resin insulating layer 24 is formed. Finally, the gold pad 25 and the power supply wiring 26 are formed by gold plating to obtain the first wiring board 10.
第２の工程ではアルミニウム板３０の表面に金パツド３
１を形成し、次に第４のポリイミド樹脂絶縁層３２を形
成し、続いて第３の信号配線層３３をその上に金めつき
で形成し、さらに第５のポリイミド樹脂絶縁層３４を形
成し、続いて第４の信号配線層３５をその上に金めつき
で形成し、これを覆う第６のポリイミド樹脂絶縁層３６
を形成する。そして、最後に金パツド３７をその上に形
成する。In the second step, gold pads 3 are applied to the surface of the aluminum plate 30.
1 is formed, then a fourth polyimide resin insulating layer 32 is formed, then a third signal wiring layer 33 is formed thereon by gold plating, and then a fifth polyimide resin insulating layer 34 is formed. Then, a fourth signal wiring layer 35 is formed by gold plating thereon, and a sixth polyimide resin insulating layer 36 covering this is formed.
form. Finally, a gold pad 37 is formed thereon.
第３の工程では、第２の工程で用いられたアルミニウム
板を希塩酸で溶解除去して第２の配線基板４０を得る。In the third step, the aluminum plate used in the second step is dissolved and removed with dilute hydrochloric acid to obtain the second wiring board 40.
この工程では図示せぬがアルミニウム板３０の下面に上
層より順次配線層を積層するようにしても良い。Although not shown in this step, wiring layers may be sequentially laminated on the lower surface of the aluminum plate 30 from the upper layer.
第４の工程では、第１の工程で得られた、第１と第２の
信号配線を有する第１の配線基板１０の表面の金パツド
２５と、第３の工程で得られた、第３と第４の信号配線
を有する第２の配線基板４０の表面の金パツド３１とを
金−エポキシ系接着剤を用いて接着することにより、第
１から第４までの４層の信号配線と２層の電源配線１ｇ
、２６と表層の金パツド３７の合計７層の配線層を有す
る高多層化された回路基板を得る。In the fourth step, the gold pad 25 on the surface of the first wiring board 10 having the first and second signal wirings obtained in the first step and the third gold pad obtained in the third step are removed. and the gold pad 31 on the surface of the second wiring board 40 having the fourth signal wiring are bonded using a gold-epoxy adhesive. Layer power supply wiring 1g
, 26 and a gold pad 37 on the surface layer, a highly multilayered circuit board having a total of seven wiring layers is obtained.
本実施例では、第２の工程でアルミニウム板を用いてい
るが、これを亜鉛板に替えることも可能である。In this embodiment, an aluminum plate is used in the second step, but it is also possible to replace this with a zinc plate.
第２図は、本発明の第２の実施例を示す縦断面図である
。FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention.
本実施例は、第１図に示した第１の実施例とほぼ同じ構
成であるが、各配線に金めつきの代りに銅めっきを用い
ている点と、第２の配線基板が複数の配線基板群５０，
５１，５２，５３に分割されている点と、第１の配線基
板と第２の配線基板（群）との接着に錫−鉛共晶半田を
用いている点とが異なる。This embodiment has almost the same configuration as the first embodiment shown in FIG. 1, except that each wiring uses copper plating instead of gold plating, and the second wiring board has a plurality of wirings. board group 50,
The difference is that it is divided into 51, 52, and 53, and that tin-lead eutectic solder is used to bond the first wiring board and the second wiring board (group).
次に本発明に係る多層回路基板の製造方法における製造
欠陥に起因する損失工数について例をもって説明する。Next, the loss of man-hours due to manufacturing defects in the method for manufacturing a multilayer circuit board according to the present invention will be explained using an example.
（例）１層あたり、１０％の製造欠陥による廃棄量がで
る配線層を、８層、積層する場合
各層での廃棄率が等しく１０％であり、各層の所要工数
も等しくＭであると仮定すれば、１枚の基板が良品であ
る期待値に１は、
Ｋ１＝０．９ ＝０．４３０
１枚の基板の損失工数の期待値Ｌ１は、１層目で廃棄さ
れるものから８層目で廃棄されるものまでの累積である
から、
Ｌ １ ＝ ”ｉ （Ｃ１，ＩＸｎＸＭＸｏ、 ９ｒ′
−’） ＝ＯＩＭ ｌ （ｎ ｘｏ、 ９”） ＝２．
２５２Ｍ従ってこの場合の、良品基板１枚あたりの損失
工数Ｌｌ／Ｋｌは、
Ｌｌ／に１＝５．２４Ｍ である。(Example) When stacking 8 wiring layers each having 10% waste due to manufacturing defects, assume that the waste rate for each layer is equal to 10%, and the required man-hours for each layer are also M. Then, the expected value of one board being good is 1, which is K1 = 0.9 = 0.430 The expected value L1 of lost man-hours for one board is 8 layers from the one that is discarded in the first layer. Since this is the cumulative amount up to what is visually discarded, L 1 = ``i (C1, IXnXMXo, 9r'
-') = OIM l (n xo, 9'') =2.
252M Therefore, in this case, the loss of man-hours Ll/Kl per one non-defective board is: Ll/=1=5.24M.
つぎに、本発明の方法にしたがって、４層づつの２枚の
基板に分割して積層し、最後に接着を行う場合は、
１枚の基板が良品である期待値に２は、Ｋ２＝０．９
＝０．６５６
１枚の基板の損失工数の期待値Ｌ２は、Ｌ ２ ＝ ：
Ｅ （０，ＩＸｎＸＭＸｏ、 ９’−’） ＝Ｏ，ＩＭ
７ （ｎ ｘｏ、 ９”）＝０．８１５Ｍ４層基板が
２枚必要であるから、最終的な良品基板１枚あたりの損
失工数は、
２ｘＬ２／に２＝２．４８Ｍ である。Next, according to the method of the present invention, when dividing and laminating two four-layer substrates and finally bonding them, the expected value of one substrate being good is 2, K2 = 0. .9
=0.656 The expected value L2 of lost man-hours for one board is L 2 =:
E (0, IXnXMXo, 9'-') = O, IM
7 (nxo, 9'') = 0.815M Since two 4-layer boards are required, the final loss of man-hours per good board is 2xL2/2 = 2.48M.
実際には、この他に、接着の工数と、接着工程における
製造欠陥に起因する損失工数が加えられる。In reality, in addition to this, the number of man-hours for bonding and the number of man-hours lost due to manufacturing defects in the bonding process are added.
これらから製造欠陥に起因する損失工数の低減がなし得
る乙とが判明する。From these results, it is clear that the loss of man-hours due to manufacturing defects can be reduced.
以上説明したように、本発明は、多層にわたる積層配線
を下層の第１の配線基板と上層の配線基板とに分け、そ
れらを同時に積層して行くことにより、積層に要する日
数をほぼ半減できるという効果がある。As explained above, according to the present invention, the number of days required for lamination can be reduced by almost half by dividing multi-layer laminated wiring into a lower first wiring board and an upper wiring board and laminating them simultaneously. effective.
また、別個に積層した第１及び第２の配線基板を接着す
ることとしたため、上述した如く、製造欠陥に起因する
損失工数を低減できるという効果がある。Furthermore, since the separately laminated first and second wiring boards are bonded together, there is an effect that the number of lost man-hours due to manufacturing defects can be reduced, as described above.
第１図は、本発明の第１の実施例を示す縦断面図、第２
図は、本発明の第２の実施例を示す縦断面図である。
１：セラミック積層配線基板
１０：第１の配線基板
１１：層間絶縁層
１２．１３，１４，１５：電源配線層
１６．１７，２５，３１，３７：金属パッド１９、２２
．２４．３２．３４．３６ ：ポリイミド樹脂絶縁層３
０：金属板としてのアルミニウム板
４０：第２の配線基板
４１：金−エポキシ系接着剤
５０．５１，５２，５３：第２の配線基板群５４：錫鉛
共晶半田FIG. 1 is a longitudinal cross-sectional view showing a first embodiment of the present invention, and a second embodiment of the present invention is shown in FIG.
The figure is a longitudinal sectional view showing a second embodiment of the invention. 1: Ceramic laminated wiring board 10: First wiring board 11: Interlayer insulation layer 12.13, 14, 15: Power supply wiring layer 16.17, 25, 31, 37: Metal pad 19, 22
．． 24.32.34.36: Polyimide resin insulation layer 3
0: Aluminum plate as a metal plate 40: Second wiring board 41: Gold-epoxy adhesive 50. 51, 52, 53: Second wiring board group 54: Tin-lead eutectic solder
Claims (1)
上に複数の配線層を形成することにより構成される多層
回路基板の製造方法において、あらかじめ多層回路基板
を下層部を構成する第１の配線基板と、上層部を構成す
る第２の配線基板とにわけ、セラミック基板上に下層よ
り順次配線層を積層して第１の配線基板を形成する第１
の工程と、アルミニウム等の金属板上に下層より順次も
しくは上層より順次配線層を積層して第２の配線基板を
形成する第２の工程と、第２の配線基板の金属板を希塩
酸により溶解除去する第３の工程と、第１の配線基板の
表面に形成された金属パッドと、第２の配線基板の表面
に形成された金属パッドとを半田付けもしくは導電性接
着剤で接着する第４の工程とを有することを特徴とする
多層回路基板の製造方法。In a method for manufacturing a multilayer circuit board formed by forming a plurality of wiring layers on a ceramic substrate using polyimide resin as an interlayer insulation, the multilayer circuit board is formed by forming a first wiring board constituting a lower layer and an upper layer in advance. A first wiring board is formed by laminating wiring layers sequentially from the bottom on a ceramic substrate.
A second step of laminating wiring layers sequentially from the bottom layer or from the top layer on a metal plate such as aluminum to form a second wiring board, and dissolving the metal plate of the second wiring board in dilute hydrochloric acid. a third step of removing the metal pads; and a fourth step of bonding the metal pads formed on the surface of the first wiring board and the metal pads formed on the surface of the second wiring board with soldering or conductive adhesive. A method for manufacturing a multilayer circuit board, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19416786A JPS6350094A (en) | 1986-08-20 | 1986-08-20 | Manufacture of multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19416786A JPS6350094A (en) | 1986-08-20 | 1986-08-20 | Manufacture of multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6350094A true JPS6350094A (en) | 1988-03-02 |
| JPH0513559B2 JPH0513559B2 (en) | 1993-02-22 |
Family
ID=16320042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19416786A Granted JPS6350094A (en) | 1986-08-20 | 1986-08-20 | Manufacture of multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6350094A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148826A (en) * | 1994-11-18 | 1996-06-07 | Nec Corp | Manufacture of polyimide multilayered wiring board |
| JPH08213757A (en) * | 1995-06-26 | 1996-08-20 | Hitachi Chem Co Ltd | Production of wiring board |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101657666B1 (en) * | 2016-06-09 | 2016-09-19 | 김옥수 | scarf |
-
1986
- 1986-08-20 JP JP19416786A patent/JPS6350094A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148826A (en) * | 1994-11-18 | 1996-06-07 | Nec Corp | Manufacture of polyimide multilayered wiring board |
| JPH08213757A (en) * | 1995-06-26 | 1996-08-20 | Hitachi Chem Co Ltd | Production of wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0513559B2 (en) | 1993-02-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |