JPS635233Y2 - - Google Patents
Info
- Publication number
- JPS635233Y2 JPS635233Y2 JP1982150039U JP15003982U JPS635233Y2 JP S635233 Y2 JPS635233 Y2 JP S635233Y2 JP 1982150039 U JP1982150039 U JP 1982150039U JP 15003982 U JP15003982 U JP 15003982U JP S635233 Y2 JPS635233 Y2 JP S635233Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- cavity
- package
- semiconductor chip
- conductive pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【考案の詳細な説明】
本案はセラミツクなどの絶縁体より成る筐体に
半導体チツプを収容するキヤビテイと導電パツド
を具備してなるリードレスパツケージに関するも
のである。[Detailed Description of the Invention] The present invention relates to a leadless package comprising a casing made of an insulating material such as ceramic and having a cavity for accommodating a semiconductor chip and conductive pads.
従来からIC、LSI等の半導体集積回路を構成す
る半導体チツプを収容するパツケージとしては、
ほぼ中央部にキヤビテイと該キヤビテイ内にワイ
ヤボンドするための導電パターンを備え、この導
電パターンを外部に導出するべく外部側面にリー
ドフレームを装備してなるデユアルインライン型
のパツケージや、平板状をなし、かつ片側面の中
央部に半導体チツプを収容するキヤビテイを形成
したセラミツク基板で、該キヤビテイの底面にマ
ウントした半導体チツプに別途用意し、セラミツ
ク基板上にガラス付けしたリードフレームにワイ
ヤボンドした後、上記セラミツク基板と同形をし
た蓋部材としてのセラミツク基板をガラス溶着し
て半導体装置を構成するようにしたサーデイツプ
型のパツケージ等が多く用いられている。 Traditionally, packages have been used to house semiconductor chips that make up semiconductor integrated circuits such as ICs and LSIs.
Dual in-line package cages include a cavity in the center and a conductive pattern for wire bonding inside the cavity, and a lead frame on the external side to lead the conductive pattern to the outside, or a flat plate type package. A ceramic substrate is formed with a cavity for accommodating a semiconductor chip in the center of one side, and the semiconductor chip is mounted on the bottom of the cavity, and the semiconductor chip is separately prepared and wire-bonded to a lead frame attached to glass on the ceramic substrate. A ceramic substrate having the same shape as the ceramic substrate as a cover member is glass-welded to form a semiconductor device, and a ceramic substrate is often used.
そのほか、上部中央部に設けたキヤビテイに半
導体チツプを収容し、該半導体チツプの各電極に
接続した外部リードを成す導電パツドを下面に配
置し、これら導電パツドを直接にプリントサーキ
ツトボード、あるいはマザーボード等にハンダ付
けして接続するようにしたチツプキヤリア型のパ
ツケージなども多く用いられている。 In addition, a semiconductor chip is housed in a cavity provided in the upper center, and conductive pads forming external leads connected to each electrode of the semiconductor chip are arranged on the bottom surface, and these conductive pads are directly connected to a printed circuit board or a motherboard. Chip carrier type packages that are connected by soldering to other parts are also often used.
ところが、叙上の如き、パツケージを用いた半
導体装置では、このような半導体装置を複数個使
用して回路装置を構成するような場合、半導体装
置をサーキツトボードなどの回路基板上に1個ず
つ平面的に配列せざるを得ないため、用いる回路
基板は必然的に大きな面積のものとなり、その結
果、電子機器全体が大型化していた。しかも一旦
半導体装置の配列を想定して設計したサーキツト
ボードでは容易に設計変更することがきわめてむ
ずかしく、また若干回路構成を変えた電子装置を
必要とするような場合、全く融通がきかないとい
う事態が発生していた。 However, with semiconductor devices using packages as described above, when a circuit device is configured using multiple such semiconductor devices, the semiconductor devices are placed one by one on a circuit board such as a circuit board. Since they have to be arranged in a flat plane, the circuit boards used inevitably have a large area, resulting in an increase in the size of the electronic device as a whole. Moreover, once a circuit board has been designed with the arrangement of semiconductor devices in mind, it is extremely difficult to easily change the design, and if an electronic device with a slightly different circuit configuration is required, there is no flexibility at all. It was occurring.
また、下面に外部導出用の導電パツドを設けた
チツプキヤリア型のものでは、回路基板に実装し
た後、作動検査を行なうような場合、半導体装置
のリード部分に検査装置(測定機器)のプローブ
を接続することが困難であり、しかも配線の手直
しをしたいような場合でも半導体装置の導電パツ
ドと容易に接続することができないため、回路の
手直しが全くきかないという不都合があつた。 In addition, for chip carrier type devices that have conductive pads on the bottom surface for external conduction, when testing the operation after mounting on a circuit board, it is necessary to connect the probe of an inspection device (measuring device) to the lead part of the semiconductor device. Moreover, even when it is desired to modify the wiring, it is not possible to easily connect to the conductive pads of the semiconductor device, so there is a problem in that the circuit cannot be modified at all.
本案は、上記の如き在来半導体装置の種々の不
都合に鑑みて、案出したもので、半導体チツプを
収容して半導体装置を構成するパツケージで多段
接続、回路の増設変更及び被検査測定プローブの
接続等が容易に行なえるように成したリードレス
パツケージをもたらさんとするものである。 This proposal was devised in view of the various inconveniences of conventional semiconductor devices as described above, and includes multi-stage connections, addition and change of circuits, and measurement probes to be tested in a package that accommodates semiconductor chips and constitutes a semiconductor device. It is an object of the present invention to provide a leadless package that can be easily connected.
以下、本案実施例を図によつて具体的に説明す
る。第1図は本案パツケージで構成した半導体装
置Mの斜視図であつて、かかる半導体装置MのX
−X線断面を示した第2図において、1はセラミ
ツクよりなるパツケージの主体を成す筐体であ
り、セラミツク生シートを積層し、焼結すること
によつて作製される。また、この筐体1のほぼ中
央部には半導体チツプSを収容するキヤビテイ2
が形成され、該キヤビテイ2の底面にマウントさ
れた半導体チツプSの各電極はキヤビテイ2内の
段部3に形成してある導電パターン4にワイヤボ
ンデイングされるが、この導電パターン4は筐体
1中に埋設され、同じく上下方向に埋設されてい
るスルーホール5に接続され、さらに該スルーホ
ール5の上端は筐体1の上面、すなわち、キヤビ
テイ2の上方周辺部に形成した上面導電パツド6
に、下端は筐体1の下面に形成した下面導電パツ
ド7に接続されているが、このスルーホール5に
は導電パターン4に接続されたものばかりでな
く、単に上面導電パツド6と下面導電パツド7を
接続したもの、あるいは上面導電パツド6と下面
導電パツド7とがスルーホール5で必ずしも接続
されておらず、いずれか一方のみが導電パターン
4とスルーホール5でもつて接続されているもの
などが混在しており、少くとも上面、下面導電パ
ツド6,7の一対以上がスルーホール5で接続さ
れている。 Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a perspective view of a semiconductor device M configured with the package according to the present invention, and the X
- In FIG. 2, which shows an X-ray cross section, 1 is a housing that forms the main body of a package made of ceramic, and is manufactured by laminating raw ceramic sheets and sintering them. In addition, a cavity 2 for accommodating the semiconductor chip S is located approximately in the center of the housing 1.
is formed, and each electrode of the semiconductor chip S mounted on the bottom surface of the cavity 2 is wire bonded to a conductive pattern 4 formed on a step 3 inside the cavity 2. The upper end of the through hole 5 is connected to the upper conductive pad 6 formed on the upper surface of the housing 1, that is, on the upper periphery of the cavity 2.
In addition, the lower end is connected to a lower conductive pad 7 formed on the lower surface of the casing 1, but this through hole 5 has not only the conductive pattern 4 connected to it, but also the upper conductive pad 6 and the lower conductive pad 6. 7 are connected, or the upper surface conductive pad 6 and the lower surface conductive pad 7 are not necessarily connected through the through hole 5, and only one of them is connected through the conductive pattern 4 and the through hole 5. At least one pair or more of the upper and lower conductive pads 6 and 7 are connected by the through hole 5.
以上のように構成されたパツケージには半導体
チツプSがキヤビテイ2内にマウントされ、導電
パターン4にワイヤボンデイングし、蓋部材8が
気密裡に施された後、半導体装置として第3図に
示す如く、プリントサーキツトボード、マザーボ
ード等の回路基板Pに設けられた所定の導電体面
に各々の下面導電パツド7,7′…がハンダ付け
されることによつて実装される。このように半導
体装置を本案に係るリードレスパツケージでもつ
て構成したものでは、第3図aのように所定の上
面導電パツド6,6′…に測定機器のプローブR
を接続し、半導体装置や電子回路の作動状況、特
性の測定、調整等を行なうことが可能であり、ま
た同図bのように予じめ回路基板Pに導電体面が
設計の時点から設けられていなかつたような場合
における回路の変更、増設等が上面導電パツド
6,6′…と回路基板P上の導電体面とワイヤW
あるいは抵抗、コンデンサなどの能動素子、ダイ
オード、トランジスタなどのコンポーネントTを
追加接続するなどして行なうことができる。 In the package constructed as described above, a semiconductor chip S is mounted in the cavity 2, wire bonded to the conductive pattern 4, and a lid member 8 is applied in an airtight manner, after which the semiconductor chip S is assembled as a semiconductor device as shown in FIG. The lower conductive pads 7, 7', . . . are mounted by soldering to a predetermined conductive surface provided on a circuit board P such as a circuit board P, a printed circuit board, a motherboard, etc. When the semiconductor device is constructed with the leadless package according to the present invention, as shown in FIG.
It is possible to measure, adjust, etc. the operating status and characteristics of semiconductor devices and electronic circuits by connecting them, and as shown in Figure b, a conductive surface is provided on the circuit board P in advance from the time of design. If the circuit is not changed or expanded, the upper conductive pads 6, 6'..., the conductor surface on the circuit board P and the wire W
Alternatively, active elements such as resistors and capacitors, components T such as diodes and transistors may be additionally connected.
さらに同図cのような回路基板Pに半導体装置
がそれ以上実装不可能な場合あるいはスペースの
有効利用を図りたいような場合には半導体装置M
の上面導電パツド6,6′…と他の半導体装置
M′の下面導電パツド7,7′…をそれぞれ接続す
ることによつて半導体装置の多段設置することが
できる。 Furthermore, if it is impossible to mount any more semiconductor devices on the circuit board P as shown in c in the same figure, or if you want to make effective use of space, the semiconductor device M
Top conductive pads 6, 6'... and other semiconductor devices
By connecting the lower conductive pads 7, 7', . . . of M', it is possible to install semiconductor devices in multiple stages.
以上のように本案によれば収納した半導体チツ
プの電極と接続し導出するリード電極として下面
導電パツド、上面導電バツドの双方もしくは一方
に接続され、または半導体チツプの電極とは接続
されることなく、上、下導電パツド同士をスルー
ホールで接続したものを具備したパツケージであ
ることから、半導体チツプを収納して半導体装置
を構成したものにあつては下面導電パツドによつ
て回路基板に接続し、上面導電パツドを利用して
測定器のプローブを接ぎ電子回路装置の作動検
査、調整等を容易に可能ならしめると共に回路機
能の変更、増設等も可能となり、さらに半導体装
置を多段実装することによつて限られたスペース
で最大の機能を発揮させることができるなど多く
の作用効果をもたらすことができる。 As described above, according to the present invention, the lead electrode is connected to the lower conductive pad and/or the upper conductive pad as a lead electrode connected to the electrode of the housed semiconductor chip, or is not connected to the electrode of the semiconductor chip. Since this is a package equipped with upper and lower conductive pads connected to each other through a through hole, if a semiconductor device is configured by housing a semiconductor chip, it is connected to the circuit board by the lower conductive pad, Using the conductive pad on the top surface to connect the probe of a measuring instrument, it is possible to easily test and adjust the operation of electronic circuit devices, as well as to change and expand circuit functions.Furthermore, by mounting semiconductor devices in multiple stages, it is possible to easily test and adjust the operation of electronic circuit devices. It can bring about many effects, such as being able to maximize functionality in a limited space.
第1図は本案パツケージで構成した半導体装置
の斜視図、第2図は第1図におけるX−X線断面
図、第3図a,b,cは本案パツケージを用いた
半導体装置を回路基板に実装した態様例を示す側
面図である。
1:筐体、2:キヤビテイ、3:段部、4:導
電パターン、5:スルーホール、6,6′:上面
導電パツド、7,7′:下面導電パツド、M,
M′:半導体装置、S:半導体チツプ。
Figure 1 is a perspective view of a semiconductor device constructed using the package of the present invention, Figure 2 is a sectional view taken along the line X-X in Figure 1, and Figures 3 a, b, and c show the semiconductor device using the package of the present invention on a circuit board. It is a side view which shows the example of an implemented aspect. 1: Housing, 2: Cavity, 3: Step, 4: Conductive pattern, 5: Through hole, 6, 6': Top conductive pad, 7, 7': Bottom conductive pad, M,
M': semiconductor device, S: semiconductor chip.
Claims (1)
プを気密封止するキヤビテイを備えるとともに上
面及び下面の各々に複数個の上面導電パツド、下
面導電パツドを配設し、これら両パツドの少なく
とも1対がスルーホールで相互に接続された複数
個のリードレスパツケージを、一方のリードレス
パツケージにおいてスルーホールで接続された上
面導電パツドと他方のリードレスパツケージにお
いてスルーホールで接続された下面導電パツドと
が直接、接続するように多段に接続して成るリー
ドレスパツケージの多段構造。 The ceramic housing has a cavity for hermetically sealing the semiconductor chip in the center thereof, and a plurality of upper conductive pads and lower conductive pads are arranged on each of the upper and lower surfaces, with at least one pair of these pads being through-holes. A plurality of leadless packages interconnected by holes are directly connected to the top conductive pad connected by the through hole in one leadless package and the bottom conductive pad connected by the through hole in the other leadless package. A multi-stage structure of leadless packages that are connected in multiple stages.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982150039U JPS5954938U (en) | 1982-10-01 | 1982-10-01 | Multi-stage structure of leadless package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982150039U JPS5954938U (en) | 1982-10-01 | 1982-10-01 | Multi-stage structure of leadless package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5954938U JPS5954938U (en) | 1984-04-10 |
| JPS635233Y2 true JPS635233Y2 (en) | 1988-02-12 |
Family
ID=30332882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982150039U Granted JPS5954938U (en) | 1982-10-01 | 1982-10-01 | Multi-stage structure of leadless package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5954938U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5024317B2 (en) * | 2002-03-25 | 2012-09-12 | セイコーエプソン株式会社 | Electronic component and method for manufacturing electronic component |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59133B2 (en) * | 1979-12-21 | 1984-01-05 | 富士通株式会社 | Multi-chip semiconductor package |
| JPS592146U (en) * | 1982-06-28 | 1984-01-09 | 富士通株式会社 | Electronic component package |
-
1982
- 1982-10-01 JP JP1982150039U patent/JPS5954938U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5954938U (en) | 1984-04-10 |
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