JPS6352475A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device whose cut-off endurance capability is big by a method wherein an electrode region functioning as a floating gate is provided so that other characteristics such as an ON voltage, etc. are not affected. CONSTITUTION:An electrode region 3b is separated from a gate electrode 3a and functions as an electrical conductor to connect a p base layer 13 in the transverse direction. The region is in a floating state without being connected with the outside and functions as a floating electrode. When a conductive region is shifted toward the side of the floating gate, the coupling potential of an n emitter 14 near the floating gate 3b and a p base layer 13 is increased, and this coupling potential is transmitted to the floating gate 3b. In this manner, all the coupling potentials of a unit GTO (gate turn-off thyristor) having the floating gate 3b are reduced by the floating gate 3b and become equipotential. Because the coupling potential is a value which is determined by the current density, the situation that all the potentials become equipotential means that the parallel function at the end of the turn-off is equalized and, as a result, the cut-off endurance capability is increased substantially.

Description

[Detailed Description of the Invention] [Field of Industrial Application] Is the invention applicable? The present invention relates to a semiconductor device that can be turned on and turned off by a No. 11 signal, and particularly relates to a structure of a semiconductor device suitable for increasing maximum cut-off withstand capability when increasing JR.

[Conventional technology]

Conventionally, semiconductor devices such as large-capacity gate turn-off thyristors (hereinafter abbreviated as GT○) and transistors have an n-emitter layer consisting of one or more elongated strips of approximately constant width, and an adjacent base layer. The base layer is exposed on one main surface of the semiconductor substrate together with the base layer, one main electrode is in low-resistance contact with each strip-shaped region, and the base layer is constrained to substantially surround each strip-shaped region. A configuration in which the II electrode is in low resistance contact, the other main electrode is in low resistance contact with the other main surface of the semiconductor, and each electrode is connected to a pair of main terminals and a control terminal is widely used. There is.

The turn-off operation in the above-mentioned conventional semiconductor device will be explained below using GTO as an example. G having the above structure
As is well known, the turn-off operation of the TO is achieved by quickly expelling excess carriers such as electrons and holes accumulated in the semiconductor substrate to the outside using a negative gate current.

Therefore, in order to make it as easy as possible to extract the gate current from the current conduction region, we adopted an elongated strip-shaped cathode emitter layer (hereinafter abbreviated as unit GTO) structure surrounded by gate electrodes as described above. A large number of these are arranged in parallel within the semiconductor substrate depending on the current capacity.

By the way, as a unit GTO arrangement suitable for large capacity storage,
Conventionally, structures have been devised in which multiple rings are arranged concentrically within a semiconductor substrate. (For example, JP-A-1@56-13
However, as the shape of the semiconductor substrate becomes larger, the desired maximum breaking current cannot be obtained even if the number of unit GTOs is increased. is occurring.

Thus, the maximum breaking current is in units of GTO
The reason why the number of GTOs does not increase in proportion to the number of GTOs is that as the diameter of the semiconductor substrate becomes larger, the non-uniformity of the turn-off operation of the unit GTO within the plane of the semiconductor substrate increases. This is because current is transferred from the unit GTO that was turned off first, causing current concentration.

Furthermore, there are two reasons why the non-uniformity of the turn-off operation among the unit GTOs in the semiconductor substrate becomes large. One is that the variation in the characteristics of the unit GTOs themselves becomes large. This is because when a semiconductor substrate has a large diameter, variations in carrier lifetime increase due to thermal distortion caused by the substrate itself and the manufacturing process.

Another cause is that the gate current distributed to each unit GTO is non-uniform due to the impedance of the control electrode. As mentioned above, Daeong IG
In the TO, one main electrode and one electrode are exposed on one main surface, and each electrode is connected to an external terminal by pressure welding with low resistance. In this case, to press the two together on the entire surface, it is necessary to miniaturize the pressure contact electrode, and it is difficult to align them, so only the main electrode is pressure-welded on the entire surface, and the control
8i is connected to an external terminal by partial pressure welding. For this reason,
The gate current of a unit GTO further away from a nearby unit GTO that is partially pressure-welded has a longer distance to flow through the control electrode provided on the semiconductor substrate, and due to the difference in impedance between them, the gate current of each unit GTO is Unit GTO
This causes non-uniformity in the gate current flowing through the gate.

Due to the above-mentioned factors, the conventional structure has a problem in that even if the diameter of the semiconductor substrate is increased, a large cut-off withstand capacity cannot be obtained.

As a means to solve such problems, Japanese Patent Application Laid-Open No. 58-2
As described in No. 06159, there is a structure in which the width of the strip-shaped n emitter layer becomes narrower as the distance from the gate current input section increases! ! It is being proposed.

This structure reduces the non-uniformity of the distributed gate current to the unit GT
By creating differences in the ease of turn-off of ○, it is attempted to make the turn-off characteristics of the entire device uniform.

However, with this method, variations in device characteristics are not considered, and the on-voltage is higher than in the conventional example.Furthermore, if there are variations in the turn-off characteristics of the unit GTo, a difference will occur in the gate current. Regulation? '! A difference occurs in the voltage drop between the 11m poles, which ultimately affects the distribution of gate current.These effects are so great that as the diameter increases, the interrupting capability may actually decrease.

[Problem to be Solved by the Invention 3] As mentioned above, in the prior art, the distribution of the gate tX is changed depending on the impedance of the control electrode, and even if the diameter is increased due to variations in the element characteristics, the interruption resistance is There was a problem that a large semiconductor control device could not be obtained.

An object of the present invention is to provide a semiconductor device having a press-contact type self-shielding 1ilT function, and in particular, to provide a semiconductor device having a large shutoff capability without affecting other characteristics such as on-voltage.

[Means for solving problems]

The above purpose is to place an electrode in a predetermined region of a semiconductor layer in a rectangular shape close to one side in the width direction so that an electrode that is not connected to the outside is also The impedance between these predetermined strip regions and the seed region is higher than the impedance between these strip regions and the control electrode.

[Effect]

In the above predetermined strip-shaped regions, only one side in the width direction serves as a current path from the control electrode, so the current is concentrated only in these strip-shaped regions, and after that, the above-mentioned t
Since the seed regions equalize the parallel operations in these predetermined strip-shaped regions, a large shielding capacity can be obtained.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be explained in detail below using illustrated embodiments.

Figures 1 to 3 show an example in which the present invention is applied to a GTO.
This is a diagram showing the cathode side plane pattern of O divided into four halves.
Figure 2 is an enlarged view of a part of the gate connection section C, .
C! This is a case where the unit GTO array is arranged in a ring shape and in the middle of a unit GTO array arranged in multiple concentric circles. 3 is a sectional view taken along line AA' in FIG. 1.

As is well known to those skilled in the art, and as can be seen in the cross-sectional view of FIG. 3, inside the semiconductor body 1 there is a p-emitter layer 11. n
Base layer 12. P base layer 13° and n emitter layer 1
4 is formed, and a pn junction necessary for thyristor operation is formed between each layer. An anode electrode 20 is electrically connected to the p emitter layer 11, a cathode II electrode 2 is electrically connected to the n emitter layer 14, and a gate electrode 3a is electrically connected to the p base WJ 13.

A control gate current is supplied from gate connections C1 and C2, and these connections C, , C□ are connected in parallel through external terminals. The electrode region 3b is separated from the gate electrode 3a, serves to connect the p base layer 13 horizontally, and is floating without being connected to the outside.

Therefore, we will call this a float gate.

Next, the turn-off operation of the CTO having the structure shown and described above will be described.

In the state immediately before the off signal is input to the GTO, the JBW flow is flowing to each unit GTO as determined by the variation in characteristics. When the OFF 1 word is input from such a state, the unit GTO having the float gate 3b will switch to one of the date terminals FM3a.
Since only carriers are extracted, turn-off is delayed compared to the unit GTo of a normal gate structure. The turn-off delay in this case is sufficiently larger than the difference in turn-off time caused by variations in the characteristics of normal unit GTOs, and the final turn-off current is taken care of by the unit GTO having the float gate 3b.

Since the unit GTO having the float gate 3b extracts carriers only from one gate tila,
The conduction region within the unit CTO is turned off after being moved toward the float gate 3b side.

Here, at the stage where the conduction region is moved toward the float gate side, the n emitter 14 near the float gate 3b
The junction potential of p base 13 rises, and the junction potential is transmitted to float gate 3b. In this way, the junction potential of all unit GTOs having the float gate 3b is
It is short-circuited at float gate 3b and has an equal potential. The junction potential is a value determined by the current density, and the fact that they become equal potential means that the parallel operations at the end of turn-off are equalized, and as a result, the interruption capability is greatly increased.

The reason is as follows. In other words, the instantaneous interruption resistance of the nested GTo is very large, for example, 2000A class G
The cutoff capacity of TO is 1/2 of the unit GTO that constitutes it.
This is because it is sufficient that about 0 of them operate evenly in parallel.

Note that it is also conceivable that all unit CTOs of the large-capacity GTO be constructed of float gates 3b.

However, providing a large number of gate connection parts will make the structure too complicated, and if you try to make it without increasing the number of gate connection parts, the arrangement of the gate electrode 3a, which is the gate input to the array unit GT○, away from the gate connection part. As a result, the difference in electrode resistance between the arrays becomes too large, resulting in uneven parallel operation of the unit GTOs between the arrays.

Further, in contrast to the above embodiments, it is also conceivable to provide a float gate on the outermost periphery or the innermost periphery farthest from the gate connection portion. This method can provide the same effect as the present invention if the characteristics of the unit GT◯ are approximately equal. However, in reality, there are variations in characteristics, and due to these variations in characteristics, the gate current from the other gate electrode 3a of the unit GTO having the float gate 3b differs even within the array ring. Even if the unit GTO has the same function, it will interfere with parallel operation, and sufficient effects cannot be obtained.

Therefore, in order to avoid the influence of such characteristic variations of the unit GTO, in the above embodiment, the unit GTO having the float gate 3b is provided near the gate connection portions C1 and CI. That is, if the resistance of the gate electrode 3a is small, it will not act as a shunt resistance when supplying gate current, and the gate current will be freely distributed according to the turn-off characteristics of the device.

Although the embodiment has been described in the case where the gate connecting portions C, Ct are located in the middle of the array ring, even if there is only one gate connecting portion, the position is at the outermost periphery.

Alternatively, it is easy to see that the same effect can be obtained even at the innermost circumference.

Further, when the width of the strip-shaped n emitter 14 is wide, the turn-off of the unit GT◯ having the float gate 3b is much delayed than that of the unit GTO whose gate is surrounded by the pole 3a. If this difference in turn-off is too large, the generated loss of the unit GTO having the float gate 3b will increase, so in that case, the width of the n emitter should be narrowed. GT○
Therefore, the width of the other n emitters 140 may be increased to a point where the turn-off time is equal to or slightly shorter than the turn-off time, thereby lowering the on-voltage of the entire element.

In the above description, the present invention has been explained using an example in which the present invention is applied to a GTO, but it goes without saying that the present invention is not limited to this and can be implemented, for example, as a semiconductor device such as a transistor. .

〔Effect of the invention〕

As explained above, according to the present invention, sufficient cut-off withstand capability can be provided with a simple configuration of providing an electrode N region that functions as a float gate, and the increase in cut-off withstand capability due to the enlargement of the element can be fully utilized. , a semiconductor device with large capacity can be easily obtained.

[Brief explanation of drawings]

FIG. 1 shows a GTO which is one implementation of a semiconductor device according to the present invention.
2 is a partially enlarged view of FIG. 1, and FIG. 3 is an explanatory diagram showing the cathode side plane pattern divided into four halves. FIG. 3 is a partial enlarged view of FIG.
It is a sectional view taken along the A' line. DESCRIPTION OF SYMBOLS 1... Semiconductor base, 2... Cathode electrode, 3a...
・Gate electrode, 3b...Float gate, 11...
p emitter layer, 12...n base layer, 13...p base layer, 14...n emitter layer, 20...anode ii, c. C2...Gate connection part. Figure 1/-----$4a Grave rest 2----One cantilever diameter 3a---One rotor Kameishisha 3b---Float gate Ct, Cz =-勺゛゛-Toki spicy 5-socket eaves Figure 2 Noto 1-P emitter 1 reader 1 12----n'r-su layer 13----P'':-su 1 14-----n emitter, 1 20----7 No 1" Warm Hitoshi Figure 3

Claims (1)

[Scope of Claims] 1. A semiconductor substrate comprising at least three layers of semiconductor layers having alternating conductivity types, wherein the outermost layer of the semiconductor layer on one main surface of the semiconductor substrate is formed into a plurality of strips. An intermediate layer formed as a region and in contact with the outermost layer is exposed on the one main surface so as to surround the strip-shaped region, and is formed on the other main surface of the plurality of strip-shaped regions and the semiconductor substrate. In the semiconductor device, the main electrode is in low-resistance contact, the control electrode is in low-resistance contact with the exposed portion of the intermediate layer, and the control electrode has a lead connection region for external control input. A common electrode area is provided for a plurality of strip-shaped regions close to the lead connection region among the plurality of strip-shaped regions, close to one side in the width direction of each of these strip-shaped regions. , characterized in that the impedance appearing between each of the plurality of strip-shaped regions and the electrode region is higher than the impedance appearing between each of these strip-shaped regions and the control electrode. Semiconductor equipment. 2. According to claim 1, the width of the strip-shaped region in which the electrode regions are formed close to each other is narrower than the width of the remaining strip-shaped regions. Semiconductor equipment.