JPS635280A - Ic testing apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an IC testing device for testing an IC (semiconductor circuit) that takes a logical value, and in particular, the invention relates to an IC testing device for testing an IC (semiconductor circuit) that takes a logical value, and in particular, to The present invention relates to an IC testing device suitable for a test that proceeds to the next test step when the expected value is matched.

[Conventional technology]

As described in Japanese Patent Application Laid-Open No. 55-55254, the conventional device includes a pattern file storing input pattern patterns and expected patterns, and a command section storing instructions for controlling the pattern file, in a pattern generation circuit. , and an operand section in which data corresponding to the contents of the command section are stored, and the test waveform generation circuit generates the match test pattern data according to the specification of the control file while referring to the response from the IC under test. by supplying −
I was conducting a qualifying exam. Here, the - matching test means that the expected value data generated from the above pattern file and the tested I
This is a test that proceeds to the next test step if the responses from C match, and is sometimes performed when testing an IC whose circuit cannot be initialized. Therefore, in the -match test, it is necessary to supply the same pattern data to the test waveform generation circuit in four chronological order until the above-mentioned -match is obtained. It is called.

[Problem that the invention seeks to solve]

In the prior art described above, no consideration was given to the generation of invalid test cycles due to the pipeline register interposed between the pattern generation circuit and the test waveform generation circuit.

Problems with this conventional device will be explained with reference to FIGS. 5 and 6. FIG. 5 shows a four-stage pipeline register 502 between a pattern generation circuit 501 and a test waveform generation circuit 506.
, 505, 504, and 505, and FIG. 6 is a time chart of the valley signals. In the illustrated example, the depth of pattern data for matching test generated from the pattern generation circuit 501 is Pa, PI
, P2 is for 3 cycles, and 3 times from N cycle to N+8 cycle (N~N+2.N+3
~N+5. 3 times (N+6 to N+9). Here, a case will be described in which, for example, a match is found using the second match test pattern data generated between the N+3 to N+5 cycles, and the - match test ends. In the illustrated example, a four-stage pipeline register 5 is provided between the pattern generation circuit 501 and the test waveform generation circuit 506.
02 to 505, the second matching test pattern data generated by the pattern generation circuit 501 in the N+3 to N+5 cycles is transferred to the test waveform generation circuit 506.
is supplied to the N+7th to N+9th after 4 cycles.
In the cycle.

Therefore, the match/mismatch signal 509, which is a signal indicating that a match has been obtained, is input to the pattern generation circuit 501 after the N+9th cycle, and from the N+5th to the N+th cycle.
For nine cycles, the pattern generation circuit 501 continues to generate matching test pattern data, and the pipeline register 5
This match test pattern data is held in 02 to 505, respectively. Therefore, in the four cycles after the N+9th cycle in which a negative match is obtained, the match test pattern data held in the pipeline registers 502 to 505 is supplied to the test waveform generation circuit 506, and the pattern data for the normal test is supplied to the test waveform generation circuit 506. There is a problem in that it is impossible to supply butter/data (Kl in FIG. 6) at the same time as the completion of the matching test, and a cycle corresponding to the number of stages of the pipeline register becomes an invalid test cycle.

An object of the present invention is to provide an IC that can prevent the occurrence of invalid test cycles due to the intervention of the pipeline register when performing a normal test subsequent to a pass test, thereby improving test efficiency. The purpose is to provide test equipment #L.

[Means for solving problems]

The above purpose is to store and hold the pattern data for the -matching test on the output side of the final stage of the pipeline register interposed between the pattern generation circuit and the test waveform generation circuit, and to keep the pattern data input until the end of the test. This is achieved by providing a matching test pattern data holding circuit that can repeatedly output data in chronological order.

[Effect]

The above-mentioned pattern data holding circuit for match test provided on the output side of the final stage of the pipeline register detects a match every time the pattern data for match test is inputted from the pattern generation circuit, and ends the match test. a control unit a1g that stores and repeatedly outputs the input match test pattern data in accordance with the input chronological order, and at the same time temporarily stops the pattern generation circuit from proceeding to the next pattern data generation cycle; Sends a control signal that prohibits the capture of data in the pipeline register, and
- At the end of the test, the above-mentioned stop and prohibition are canceled and pattern data generation is restarted from the next cycle after the stop. From this point on, valid pattern data is always stored in the pipeline register interposed between the pattern generation circuit and the test waveform generation circuit. It is possible to prevent invalid test cycles occurring after SA ends.

〔Example〕

Hereinafter, one embodiment of the present invention will be described using FIGS. 11g1 to 6. FIG. 1 is a block diagram, FIG. 2 is a block diagram showing details of the matching test pattern data holding circuit in FIG. 1, and FIG. 5 is a time chart of signals of each part for explaining its operation.

In FIG. 1, 101 is a pattern generating circuit, and 102 is a matching test pattern holding circuit provided in the present invention. - The matching test pattern holding circuit 102 transfers pattern data 107 used for test waveform generation in the test waveform generation circuit 103 to pipeline registers 120, 121, . . . , 12 from the pattern generation circuit 101.
2i, and using the control signals 108 to 110 from the pattern generation circuit 101 and the like, during a match test, the comparison circuit 105 compares the output of the IC under test 104 and the target value data 116 from the pattern generation circuit 101. The input pattern data 107 is repeatedly output until they match, and at the same time, a hold signal 112 is output that prevents the pattern generation circuit 101 from generating pattern data for the next step. Also, during a normal test, the input cover pattern data 107 is used as a test waveform generating circuit 10.
3 through the signal line 115. Note that 106 is a timing generation circuit that generates a basic cycle clock 117, 114 is a coincidence signal output from the comparison circuit 105, and 115 is a coincidence signal of opposite polarity.

The details of this matching test pattern holding circuit 102 are explained in the second section.
This will be explained using a block diagram. In FIG. 2, signals corresponding to those in FIG. 1 are given the same reference numerals. In the following explanation, the depth of the match test pattern data that can be stored in the match test pattern holding circuit is 4 steps, and 3 steps of match test pattern data are input and repeated until a match occurs. shall be.

As shown in FIG. 2, the match test pattern holding circuit (102 in FIG. 1) of the embodiment includes an input selection control circuit 201, a match test pattern output circuit 202, a pattern selector 203, and a hold signal. It is composed of a generation circuit 204.

The input selection control circuit 201 has a counter 205 . Decoder 206. Four control gates 207 to 210 are formed, -
The mode signal 110 and the basic cycle clock 117 are input to identify the normal g@ mode and the normal g@ mode, and -
In the match test mode, the pattern data 1078 - control signal 24 for importing into the match test pattern output circuit 202
Outputs 6 to 249. The mode signal 110 is the pattern data 10 from the pattern generation circuit (101 in FIG. 1).
When 7 is pattern data for a match test, the signal has a logic level "1", and when it is pattern data for a normal test, it has a logic level 10". Outputs 240 and 241 of the counter 205 in the input selection control circuit 201
The outputs 246-249 of the control gates 207-210 may be as shown in FIG. 4, for example.

The matching test pattern output circuit 202 has an input selector 2
11-214. D7 rib 70 rib 215-218° output selector 219. output selector control counter 220,
There are four counter control gates 221 and 222.

The input selectors 211 to 214, as shown in FIG.
Only when the mode signal 110 is 11'', the selection control signals 246 to 249 sequentially output the matching test patterns to the D flip-flops 215 to 218. As shown in A, the pattern data PO+Pl+P2 are sequentially output to the D flip 70 knobs 215, 216, and 217.The mode signal 110 becomes 10", and the pattern data 107 input to the pattern output circuit 202 for -match test is normal test. For butter/data (@Kt in Figure 3)
In this case, input selectors 211-214 all select output signals 250-253 of D flip-flops 215-218. That is, D flip-flops 215 and 216
, 217 are the periodic clocks 117 (as shown in FIG.
According to Figure 3a), the - matching test pattern data (
Figure 3G,)1. I) and output it.

In the output selector 219, according to the value of the count output signal 254.255 of the 2-bit output selector control counter 220, as shown in FIGS.
216, 217 output signals 250, 251, 2
52 and outputs -C. The reset input signal 257 of the output selector control counter 220 is input as follows.
When the falling edge 109 of the mode signal is input by the counter control gates 221 and 222, or when the mode signal 110 is 10'', a match/non-match signal is sent from the comparison circuit (105 in Figure J!1). This is a case where the falling edge of Q (E in FIG. 3) with "1" is input. But-
Therefore, in this embodiment, the reset input signal 2 shown in FIG.
57, the fourth. 7th. At the beginning of the 9th cycle, 5
It is reset as shown in v13 Figure F. Note that the edge detection circuit 258 detects the -match/dismatch number 114 (Fig. 3E).
) is used to detect the falling edge of

The hold signal generation circuit 204 prohibits the pattern generation circuit (101 in FIG. 1) from generating pattern data for the normal test during the period when the -match test is performed, and controls the step so that the steps are not updated. A hold signal 112 is generated. The hold signal generation circuit 204 includes a cycle number storage counter 227 . Reset control gates 224-226
, 229, R87 lip 70 knob 2 for set control
28. Set control gate 230.

Edge detection circuit 231. It is composed of a hold control RS flip-flop 232. The set control RS clip-flop 228 is set by the rising edge of the mode signal 108, and is reset when the match/mismatch signal 114 is 11" (when there is no match). Therefore, in the example shown in FIG. The match/mismatch signal 114 (E in Figure 3) is "1" in the second cycle, but the mode signal 110 (B in Figure 3) is 11", so it is set at the beginning of the fourth cycle. It is. On the other hand, the mode signal 110 is input to the enable input of the cycle number storage counter 227, and the cycle clock 117 is counted while this signal is 11''.

Therefore, as shown in the third diagram, the outputs 259 and 260 of the cycle number storage counter 227 are %1 because counting is performed during the period when the pattern data for matching test (FIG. 3A) Pc to P2 is output. //, %o'', and the counting ends, and the output value indicates the number of cycles in which the matching test pattern data was output.

Gates 224 to 226 are output selector control counter 2
20 and the output of the cycle number storage counter 227, as shown in FIG.
In this example, when the output of the output selector control counter 220 becomes ``1'' and ``0'', that is, the output 256 of the match test pattern output circuit 202 is the last match test pattern ($3). When outputting P2) in J,
- is detected. At this time, the mode signal 110 is 10"
(Other than the 1st to 3rd cycles in Figure 3)
The gate 229 opens and the opposite polarity match (g1) is opened.
15 (FIG. 3e) is 11" (if a match is detected by the comparison circuit 105), the output of the gate 229 is 11".
becomes. The edge detection circuit 261 is for detecting the rise of the output signal of the gate 229, and as shown in FIG. 3N, the hold control R87 lip-flop 232 is reset by the output of the edge detection circuit 231.
A hold signal 112 (fifth centroid) is created and supplied to the pattern generation circuit 101.

The pattern selector 203 switches and outputs the pattern data 107 and the output signal 256 (FIG. 5J) from the matching test pattern circuit 202 in response to the hold signal 112. As shown in Figure 3 P,
When the hold signal is 11'', the output 256 from the matching test pattern output circuit 202 is selected, and when it is 0, the pattern data 107 is selected and supplied to the test waveform generation circuit 105.

As described above, according to this embodiment, when performing a match test, it is possible to retain the match test pattern data generated by the pattern generation circuit until the end of the match test and repeatedly output it. Therefore, the pattern generation circuit only needs to generate matching test pattern data once, and
- During the execution test, the generation of pattern data is temporarily stopped by a control signal that prevents the pattern generation circuit from generating pattern data for the next step. , by generating the pattern data again from the next stopped step,
- It is possible to prevent invalid test cycles from occurring due to execution of compliance tests. In particular, by providing this matching test function for each test pin of the IC under test, it is possible to eliminate the occurrence of invalid test cycles when switching from matching test to normal test, and to greatly improve test efficiency. It becomes possible.

〔Effect of the invention〕

According to the present invention, the input pattern data for matching test can be stored and held, and the pattern data for matching test can be repeatedly output according to the input chronological order until the matching test is completed. It is possible to prevent the occurrence of invalid test cycles, which was a problem in the prior art, and improve test efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing details of the matching test pattern holding circuit in FIG. 1, and FIG. 3 is a time chart of various signals in FIG. FIG. 4 is a truth table of the input selection control circuit in FIG. 2, FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a time chart of the valley signal in FIG. [Explanation of symbols] 101... Pattern generation circuit. 103...Test waveform generation circuit. 102...-pattern holding circuit for compliance test. 104... IC under test, 105... Comparison circuit. 106...timing generation circuit. 107...Pattern data. 110...Mode signal, 112...Hold signal. 117...Basic cycle clock. 201...Input selection control circuit. 202... - Compliance test pattern output circuit 203...
pattern selector. 204...Hold signal generation circuit no go 1 pa 1 \- to %+1114--Thing LIA, Ichitsumi IC1
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Claims (1)

[Claims] 1. Means for generating pattern data and expected value data, means for generating a test waveform from the pattern data and supplying it to the IC under test, and output from the IC under test and the expected value data. In an IC testing device, the IC testing apparatus includes means for holding and storing a specified series of pattern data among the pattern data for a specified period of time, and a means for holding and storing a specified series of pattern data among the pattern data for a specified period of time. An IC testing device characterized by comprising: means for repeatedly outputting the pattern data in the same chronological order as the input time; and means for generating a signal for inhibiting generation of the pattern data during the period during which the pattern data is repeatedly output. 2. The IC testing apparatus as set forth in claim 1, wherein the holding storage means, the replay output means, and the inhibition signal generation means are provided for each test pin of the IC under test. IC testing equipment.