JPS6354737A - Method of packaging integrated circuit chip - Google Patents

Method of packaging integrated circuit chip

Info

Publication number
JPS6354737A
JPS6354737A JP19923486A JP19923486A JPS6354737A JP S6354737 A JPS6354737 A JP S6354737A JP 19923486 A JP19923486 A JP 19923486A JP 19923486 A JP19923486 A JP 19923486A JP S6354737 A JPS6354737 A JP S6354737A
Authority
JP
Japan
Prior art keywords
chip
substrate
pads
integrated circuit
circuit chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19923486A
Other languages
Japanese (ja)
Inventor
Fumihiro Ogawa
小川 文博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19923486A priority Critical patent/JPS6354737A/en
Publication of JPS6354737A publication Critical patent/JPS6354737A/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To connect pads directly, and to enable the high density packaging of an IC chip by connecting an electrode on the IC chip to a wiring on a substrate, to which the IC chip is packaged, by particulates having conductivity and fixing the IC chip with insulating adhesives. CONSTITUTION:Resin spheres 2 having diameters (5-25mum) of one tenth or less of IC pad pitches are sprayed with an air gun against an IC-chip packaging substrate, in which substrate pads 1 are fitted where opposite to IC pads 4 for an IC chip 3, thus uniformly dispersing the resin spheres 2. The surfaces of the resin spheres 2 are plated previously with nickel and gold through an electroless plating method. The IC chip 3 and the pads 1 for the substrate are faced oppositely, IC chips 3 is judged whether nondefective or defective with the IC chip 3 and the pads 1 for the substrate faced oppositely and pressure- welded through the resin spheres 2, and the defective IC chips 3 are exchanged. The periphery of the IC chip 3 is heated and fastened by thermosetting epoxy adhesives 5 under the state in which the IC chip 3 is pressure-welded on the nondefective IC chips 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ICチップの実装方法に関し、特にICチッ
プとICチップを実装する基板とを接続する方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for mounting an IC chip, and particularly to a method for connecting an IC chip and a substrate on which the IC chip is mounted.

〔従来の技術及び問題点〕[Conventional technology and problems]

ICチップの実装方法の従来の技術としては、ICチッ
プを基板上にダイボンデングし、ICチップのパッドを
金線あるいは、アルミニウム線で接続するワイヤーボン
ディング法が知られている。
As a conventional technique for mounting an IC chip, a wire bonding method is known in which the IC chip is die-bonded onto a substrate and the pads of the IC chip are connected using gold wire or aluminum wire.

しかしながら、−枚の基板に複数のICチップをしかも
ICチップのパッド数が100を超える様な場合の実装
には、接続に時間がかかること、及び不良ICチップの
交換が難かしい等の問題があった。この技術にかわる技
術としてTAB法が提案され、一部実用化されている。
However, when mounting multiple IC chips on one board and the number of IC chip pads exceeding 100, there are problems such as the time required for connection and the difficulty in replacing defective IC chips. there were. The TAB method has been proposed as an alternative to this technique, and has been partially put into practical use.

この方法は、ICパッド上に金バンプを形成し、基板の
パッドを、ICパッドと対面する様にパターン化し、バ
ンプを加熱、加圧し、溶接するものである。しかしなが
ら、バンプ付ICチップは、高価であることから、その
用途は限られている− 最近、液晶ディスプレイの分野あるいはファクシミリ用
密着形センサー・サーマルヘッドの分野において、ガラ
ス基板、プリント基板等の基板上に複数個のICチップ
を高密度に実装する技術が求められているが、上述の従
来技術では作業時間。
In this method, gold bumps are formed on IC pads, the pads of the substrate are patterned so as to face the IC pads, and the bumps are heated, pressurized, and welded. However, since bumped IC chips are expensive, their uses are limited. Recently, bumped IC chips have been used on substrates such as glass substrates and printed circuit boards in the field of liquid crystal displays and contact type sensors/thermal heads for facsimile machines. There is a need for a technology to mount multiple IC chips at high density, but the conventional technology described above requires a lot of work time.

実装密度、コストの面で問題がある。There are problems in terms of packaging density and cost.

上述した従来のICチップの実装方法に対し、本発明の
目的は、従来の接続方法は全く異なり、従来技術の問題
点を解決するパッド接続方法を用いたICチップの実装
方法を提供することにある。
In contrast to the conventional IC chip mounting method described above, the purpose of the present invention is to provide an IC chip mounting method using a pad connection method that is completely different from the conventional connection method and solves the problems of the conventional technology. be.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明はICチップ上の電極とICチップを実装する基
板上の配線とを導電性を有する微小粒子により接続し、
絶縁性接着剤で固着する工程を含むICチップの実装方
法をその要旨とするものである。
The present invention connects electrodes on an IC chip and wiring on a board on which the IC chip is mounted using conductive microparticles,
The gist of this is a method for mounting an IC chip, which includes a process of fixing with an insulating adhesive.

導電性を有する数小粒子と絶縁性接着剤とにより■Cチ
ップと基板とを接続するために1すべでのICチップの
パッドとそれぞれ対応する基板のパッドとを一度に接続
でき、パッド数が増加してもワイヤボンディングのよう
に接続時間が増加することがなく、工程が簡略化できる
。また高価なバンプ付のICチップを用いることなく、
パッド間を直接接続できるため、通常の安価なICチッ
プを使用できる。
By using a few small conductive particles and an insulating adhesive, it is possible to connect all IC chip pads and their corresponding pads on the board at once to connect the C chip and the board, reducing the number of pads. Even if it increases, the connection time does not increase unlike wire bonding, and the process can be simplified. Also, without using expensive bumped IC chips,
Since the pads can be directly connected, ordinary inexpensive IC chips can be used.

以下、本発明について実施例を用い詳説する。Hereinafter, the present invention will be explained in detail using examples.

〔実施例〕〔Example〕

第1図は、本発明の第1の実施例の模式平面図である。 FIG. 1 is a schematic plan view of a first embodiment of the present invention.

ICチップ3のICパッド4に対面する位置に基板パッ
ド1が設けられたICチップ実装基板にICパッドピッ
チの1/10以下の直径(5〜25μm)の樹脂球2を
エアーガンにより吹き付けることによりー様に分散させ
る。この樹脂球2はあらかじめ無電解メッキ法で表面が
ニッケル・金メッキされている。樹脂球2として積木フ
ァインケミカル(株)製のミクロパール(商品名)を用
いる。次にICチップ3と基板のパッド1を対面させ樹
脂球2を介して圧接した状態でICチップ3の良否を判
定し、不良の場合は交換する。ICチップ3が良品の場
合は、ICチップ3を圧接した状態でICチップ3の周
辺を熱硬化性エポキシ接着剤5(例えば、日本ベルノッ
クス製XC−1967−1)により加熱固着する。この
熱硬化性エポキシ接着剤5は、ICチップのモールドの
役目を兼ねている。このためICチップと基板とを接続
し、両者を固定する工程とICチップのモールド工程と
を上述した一連のパッド接続工程のみにより行なえるた
め、実装工程が簡略化できる。
By spraying resin balls 2 with a diameter (5 to 25 μm) of 1/10 or less of the IC pad pitch using an air gun onto an IC chip mounting board on which a board pad 1 is provided at a position facing the IC pad 4 of the IC chip 3. Distribute to Mr. Lee. The surface of the resin ball 2 is plated with nickel and gold using an electroless plating method. As the resin sphere 2, Micro Pearl (trade name) manufactured by Blockbuster Fine Chemical Co., Ltd. is used. Next, with the IC chip 3 and the pads 1 of the substrate facing each other and press-contacted through the resin balls 2, the quality of the IC chip 3 is determined, and if it is defective, it is replaced. If the IC chip 3 is a good product, the periphery of the IC chip 3 is heat-fixed with a thermosetting epoxy adhesive 5 (for example, XC-1967-1 manufactured by Nippon Bellnox) while the IC chip 3 is pressed. This thermosetting epoxy adhesive 5 also serves as a mold for the IC chip. Therefore, the process of connecting the IC chip and the substrate and fixing them together and the process of molding the IC chip can be performed only by the above-described series of pad connection processes, thereby simplifying the mounting process.

第2の実施例では、ICチップ実装基板にガラス基板を
用い、基板パッドを酸化インジウム・スズ合金による透
明電極で形成する。第一の実施例と同様IC樹脂球を分
散させ、ICチップと基板を圧接する過程まで同じであ
るが、良品のICチップを固定する接着剤として紫外線
のエポキシ接着剤(例えば、積木ファインケミカル(株
)製フォトレークA−302)を用いる。本実施例の接
着剤は粘度が低く流動性が高い故、ICチップと基板の
間に流入される。ガラス基板の裏面より紫外線照射をし
、ICチップとガラス基板を固着する。紫外心硬化性接
着剤を使用することにより、室温で重合を起こさせるこ
とができるため、ICチップとガラス基板との間の熱膨
張係数の差による機会的ストレスが発生することもなく
、重合時間も短いため、短時間でICチップとガラス基
板を接続できる。
In the second embodiment, a glass substrate is used as the IC chip mounting substrate, and the substrate pad is formed with a transparent electrode made of an indium tin oxide alloy. The process of dispersing the IC resin spheres and pressing the IC chip and the substrate is the same as in the first embodiment, but an ultraviolet epoxy adhesive (for example, from Block Fine Chemical Co., Ltd. Photolake A-302) manufactured by ) is used. Since the adhesive of this example has low viscosity and high fluidity, it flows between the IC chip and the substrate. Ultraviolet rays are irradiated from the back side of the glass substrate to fix the IC chip and the glass substrate. By using an ultraviolet core-curing adhesive, polymerization can occur at room temperature, so there is no opportunity stress caused by the difference in thermal expansion coefficient between the IC chip and the glass substrate, and the polymerization time is shortened. Since the length is also short, the IC chip and the glass substrate can be connected in a short time.

以上の実施例において、まず樹脂球を介してICチップ
と基板とを圧接し、その後、接着剤で両者を固定してい
るため、圧接した状態でICチップの良否が判定でき、
不良の場合は容易にICチップを交換できる効果がある
In the above embodiments, the IC chip and the substrate are first brought into pressure contact via the resin sphere, and then they are fixed with adhesive, so it is possible to judge whether the IC chip is good or bad while they are in pressure contact.
This has the effect of allowing the IC chip to be easily replaced if it is defective.

以上の実施例においては、導電性を有する微小粒子とし
てミクロパールを用いたが、これはミクロパールが比較
的粒径が揃っておシ、現状では本発明に適した樹脂球で
あるためであシ、将来出現するであろう他商品の樹脂球
を用いても同様な効果が得られることは明らかである。
In the above examples, micropearls were used as conductive particles, but this is because micropearls have a relatively uniform particle size and are currently resin spheres suitable for the present invention. It is clear that similar effects can be obtained by using other resin spheres that will appear in the future.

また実施例においては、表面がニッケル・金メッキされ
たミクロパールを用いたが、このミクロパールに限らず
、表面がニッケルあるいはニッケル・金等の導電性物質
で覆われた樹脂球を用いれば同様の効果が得られる。ま
た導電性物質を樹脂中に分散させた物からなる微小粒子
を用いても同様の効果が得られる。さらにこの微小粒子
は樹脂球に限定されるものではなく、In、 Au、 
Ag、 Pd、 Pt、 Ni等の金属やグラファイト
等の導電性物質あるいはこれらの元素を含み導電性を有
する合金や化合物、またはPb−8n合金等からなる粒
子を用いても同様の効果が得られる。
In addition, in the examples, micropearls whose surfaces were plated with nickel or gold were used, but the same effect can be achieved by using not only micropearls but also resin spheres whose surfaces are covered with nickel or a conductive substance such as nickel and gold. Effects can be obtained. A similar effect can also be obtained by using microparticles made of a conductive substance dispersed in a resin. Furthermore, these microparticles are not limited to resin spheres, but include In, Au,
Similar effects can be obtained by using particles made of metals such as Ag, Pd, Pt, and Ni, conductive substances such as graphite, alloys or compounds containing these elements that have conductivity, or Pb-8n alloy. .

さらにチップのパッドと基板のパッド間には、微小粒子
が一層存在するように分散することが望ましい。これは
、粒子が多層の状態で存在すると、ICチップのパッド
間が導通されやすくなるためである。パッド上に粒子を
一層分散させるためには、微小粒子の形状が球状あるい
はこれに近い形状であればよい。このような形状を持つ
微小粒子を使用すれば、粒子相互間の縦方向の重なりが
生じにくくなシ、接触抵抗値のバラツキも押えられる。
Furthermore, it is desirable that the fine particles be dispersed so that they are more present between the pads of the chip and the pads of the substrate. This is because when particles exist in a multilayered state, electrical conduction between pads of an IC chip becomes easier. In order to further disperse the particles on the pad, the shape of the microparticles may be spherical or a shape close to this. If microparticles having such a shape are used, it is difficult for particles to overlap each other in the vertical direction, and variations in contact resistance values can also be suppressed.

この微粒子はある程度の柔軟性を持つことが望ましい。It is desirable that these fine particles have some degree of flexibility.

これはICチップのパッドと基板のパッドとをこの微小
粒子を介して圧接した時に、この粒子が変形し、接触面
積が大きくなり、接触抵抗を下げることができるからで
ある。
This is because when the pads of the IC chip and the pads of the substrate are pressed together through these fine particles, the particles deform, increasing the contact area and lowering the contact resistance.

才たこの微小粒子の直径は1〜25μm1特に5〜25
μmの間であることが望ましい。1μm以下では接触抵
抗値が大きくなりすぎ、5μm以下あるいは25μm1
以上では接触抵抗値にバラツキが生じ、また25μm以
上ではICチップのパッド間が短絡してしまう可能性が
あるからである。
The diameter of the minute particles of octopus is 1 to 25 μm, especially 5 to 25 μm.
Preferably, it is between μm. If it is less than 1μm, the contact resistance value will be too large, and if it is less than 5μm or 25μm1
This is because if the thickness is more than 25 μm, there will be variations in the contact resistance value, and if it is more than 25 μm, there is a possibility that the pads of the IC chip may be short-circuited.

以上の実施例では基板に樹脂球を分散させたが、ICチ
ップ上に分散させても同様の効果が得られろ。
In the above embodiments, the resin spheres were dispersed on the substrate, but the same effect could be obtained by dispersing them on the IC chip.

さらに、実施例においては、まず微小粒子を基板に分散
させ、その後接着剤によりICチップと基板とを固定し
たが、接着剤中に微小粒子を予め分散させたものを使用
し、ICチップと基板のパッド間の接続とICチップと
基板の同定を同時に行なってもよい。この場合工程が簡
略化される効果がある。
Furthermore, in the example, microparticles were first dispersed on the substrate, and then the IC chip and the substrate were fixed with an adhesive. The connection between the pads and the identification of the IC chip and the substrate may be performed at the same time. In this case, there is an effect that the process is simplified.

実施例では、基板上に1個のICチップを実装する場合
について説明したが、複数個のICチップを実装する場
合も同様に適用できることは明らかである。
In the embodiment, a case has been described in which one IC chip is mounted on a substrate, but it is clear that the present invention can be similarly applied to a case in which a plurality of IC chips are mounted.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は導電性を有する微小粒子
と絶縁性接着剤とKよりICチップと基板とを接続する
ために、すべてのICチップのパッドとそれぞれ対応す
る基板のパッドとを一度に接続でき、パッド数が増加し
てもワイヤポンディングのように接続時間が増加するこ
とがなく、工程が簡略化できる。また高価なバンプ付の
ICチップを用いることなく、パッド間を直接接続でき
るため、通常の安価なICチップを使用できる。
As explained above, in order to connect IC chips and substrates using conductive microparticles, an insulating adhesive, and K, the pads of all IC chips and the corresponding pads of the substrate are connected at once. Even if the number of pads increases, the connection time does not increase unlike wire bonding, which simplifies the process. Furthermore, since the pads can be directly connected without using an IC chip with expensive bumps, an ordinary inexpensive IC chip can be used.

さらに、パッド間を直接接続できるため、ワイヤーボン
ディング用の空間を取る必要がなく、ICチップを高密
度に実装できる。
Furthermore, since the pads can be directly connected, there is no need to take up space for wire bonding, and IC chips can be mounted at high density.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の第1の実施例の模式平面図である。 1・・・・・・基板パッド、2・・・・・・樹脂球、3
・・・・・・ICチップ、4・・・・・・ICパッド、
5・・・・・・熱硬化性エポキシ接着剤。 xt  l □  − 代理人 弁理士  内 原   日   。 へ、ノ ゝ 。 級ゞ゛′ド     箇1 圀
FIG. 1 is a schematic plan view of a first embodiment of the present invention. 1... Board pad, 2... Resin ball, 3
...IC chip, 4...IC pad,
5...Thermosetting epoxy adhesive. xt l □ − Agent Patent attorney Hi Uchihara. Hey, no. Class ゞ゛'do Section 1

Claims (8)

【特許請求の範囲】[Claims] (1)集積回路チップ上の電極と該集積回路チップを実
装する基板上の配線とを、導電性を有する微小粒子によ
り接続し、絶縁性接着剤で固着する工程を含むことを特
徴とする集積回路チップの実装方法。
(1) Integration characterized by including the step of connecting electrodes on an integrated circuit chip and wiring on a substrate on which the integrated circuit chip is mounted using conductive microparticles and fixing them with an insulating adhesive. How to mount circuit chips.
(2)前記接続する工程は前記チップの電極と前記基板
の配線とを、前記微小粒子を介して圧接し、その後前記
絶縁性接着剤を注入するにより固着することを特徴とす
る特許請求の範囲第1項記載の集積回路チップの実装方
法。
(2) The connecting step is characterized in that the electrodes of the chip and the wiring of the substrate are brought into pressure contact with each other through the microparticles, and then fixed by injecting the insulating adhesive. A method for mounting an integrated circuit chip according to item 1.
(3)前記接続する工程は前記微小粒子を混入した前記
絶縁性接着剤を介して前記チップと前記基板を重ねて圧
接することを特徴とする特許請求の範囲第1項記載の集
積回路チップの実装方法。
(3) The integrated circuit chip according to claim 1, wherein the connecting step involves stacking and pressing the chip and the substrate together via the insulating adhesive mixed with the microparticles. How to implement.
(4)前記微小粒子は表面がニッケルメッキあるいはニ
ッケル・金メッキされた樹脂球であることを特徴とする
特許請求の範囲第1項、第2項または第3項記載の集積
回路チップの実装方法。
(4) The integrated circuit chip mounting method according to claim 1, 2 or 3, wherein the microparticles are resin spheres whose surfaces are plated with nickel or nickel and gold.
(5)前記微小粒子はその直径が5〜25μmであるこ
とを特徴とする特許請求の範囲第1項、第2項または第
3項記載の集積回路チップの実装方法。
(5) The integrated circuit chip mounting method according to claim 1, 2 or 3, wherein the microparticles have a diameter of 5 to 25 μm.
(6)前記微小粒子は、表面がニッケルメッキあるいは
ニッケル・金メッキされた直径5〜25μm樹脂球であ
ることを特徴とする特許請求の範囲第1項、第2項また
は第3項記載の集積回路チップの実装方法。
(6) The integrated circuit according to claim 1, 2, or 3, wherein the microparticles are resin spheres having a diameter of 5 to 25 μm and whose surfaces are nickel plated or nickel/gold plated. Chip mounting method.
(7)前記接着剤は熱硬化性エポキシ系接着剤であるこ
とを特徴とする特許請求の範囲第1項、第2項または第
3項記載の集積回路チップの実装方法。
(7) The integrated circuit chip mounting method according to claim 1, 2 or 3, wherein the adhesive is a thermosetting epoxy adhesive.
(8)前記接着剤は紫外線硬化性エポキシ系接着剤であ
ることを特徴とする特許請求の範囲第1項、第2項また
は第3項記載の集積回路チップの実装方法。
(8) The integrated circuit chip mounting method according to claim 1, 2 or 3, wherein the adhesive is an ultraviolet curable epoxy adhesive.
JP19923486A 1986-08-25 1986-08-25 Method of packaging integrated circuit chip Pending JPS6354737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19923486A JPS6354737A (en) 1986-08-25 1986-08-25 Method of packaging integrated circuit chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19923486A JPS6354737A (en) 1986-08-25 1986-08-25 Method of packaging integrated circuit chip

Publications (1)

Publication Number Publication Date
JPS6354737A true JPS6354737A (en) 1988-03-09

Family

ID=16404387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19923486A Pending JPS6354737A (en) 1986-08-25 1986-08-25 Method of packaging integrated circuit chip

Country Status (1)

Country Link
JP (1) JPS6354737A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0237735A (en) * 1988-07-27 1990-02-07 Semiconductor Energy Lab Co Ltd Mounting structure of semiconductor chip
JPH0374852A (en) * 1989-08-17 1991-03-29 Canon Inc Interconnecting method for electrode terminals

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51100679A (en) * 1975-03-03 1976-09-06 Suwa Seikosha Kk
JPS51135938A (en) * 1975-05-21 1976-11-25 Seiko Epson Corp Anisotropic electroconductive adhesive
JPS5821350A (en) * 1981-07-30 1983-02-08 Seiko Epson Corp Mounting structure of semiconductor integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51100679A (en) * 1975-03-03 1976-09-06 Suwa Seikosha Kk
JPS51135938A (en) * 1975-05-21 1976-11-25 Seiko Epson Corp Anisotropic electroconductive adhesive
JPS5821350A (en) * 1981-07-30 1983-02-08 Seiko Epson Corp Mounting structure of semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0237735A (en) * 1988-07-27 1990-02-07 Semiconductor Energy Lab Co Ltd Mounting structure of semiconductor chip
JPH0374852A (en) * 1989-08-17 1991-03-29 Canon Inc Interconnecting method for electrode terminals

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