JPS6355657A - Common bus connection method - Google Patents

Abstract

PURPOSE:To secure an easy connection with a control package having a direct memory access (DMA) function by validating the output contents of an output means when a DMA permission signal is sent to a control adaptor from a microcomputer and controlling the gate of a bus driver circuit. CONSTITUTION:A common bus connection system consists of a basic unit 1 and an extension unit 2 which are connected to a common bus 10 via a connection part 16 and bus driver circuits 11-14. The unit 1 contains a microcomputer 3, control packages 5 and 6, and a bus control circuit 4. While the unit 2 includes control packages 7-9. When a DMA permission signal is given from the computer 3, the gates of circuits 11-14 are controlled.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a common bus connection method in a system using a microcomputer, etc., and in particular allows connection with an expansion unit without changing the control package. related to a common bus connection method.

[Prior art]

As computer systems expand, expansion units are often connected to a basic unit containing a microcomputer or the like via a common bus. In this case, a bidirectional bus is used as the data bus, and the expansion unit is connected via a bus driver circuit, so various connection powers for controlling this bus driver circuit M have been proposed. In particular, a connection method that allows the use of existing control packages in expansion units is becoming important in order to maintain compatibility with conventional equipment.

For example, in the method described in Japanese Patent Application Laid-Open No. 58-5821, the selection signal of the own package, which is output from the control package of the expansion unit, is connected to the bus driver circuit, and this signal controls the opening and closing of the gate of the bus driver circuit. It's in control. However, with this method, it is difficult to accommodate the control package that does not output the selection signal, and to control the gate of the bus driver circuit during direct memory access (hereinafter abbreviated as DMA) performed using the control package as a mask. is not taken into account.

[Problem to be Solved by the Invention 3] In the prior art as described above, no consideration was given to the connection of the existing control package to the expansion unit, and there was a problem with the compatibility of the control packages. Also, R
No consideration was given to gate control during DMA, which is performed using the control package in the installation unit as a mask, and D
There was a problem that a control package having an MA function could not be accommodated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a common bus connection method that can improve the above-mentioned problems, maintain compatibility of control packages, and easily connect control packages having a DMA function.

[Means to solve the problem]

In order to achieve the above object, the common bus connection method of the present invention, when connecting an existing control package, accommodates a microcomputer, etc. in a basic unit, and connects the common bus with an expansion unit containing the control package. In a bus control system performed via a bus driver circuit, a means for storing an address area assigned to a control package housed in the expansion unit, and an address area stored in the storage means and a time when the control package is accessed. The number of means for comparing the address of the control package with the number of slots in the expansion unit is equal to the number of slots in the expansion unit, and the address area stored in the storage means is compared with the address of the control package at the time of access. If the address is within the address area, a control signal is output, the control signal is connected to the bus driver circuit, and the gate control of the bus driver circuit is performed.

Furthermore, when connecting a control package having a DMA function, the common bus connection method of the present invention accommodates a microcomputer, a direct memory access controller, etc. in a basic unit, and performs direct memory access (hereinafter referred to as DMA). In a bus control system in which a common bus connection with an expansion unit accommodating a control adapter equipped with a mask function (omitted) is made via a bus driver circuit, the DMA access corresponds to a DMA channel of the bus control system, and the DMA access is Means for storing and outputting information indicating whether to read or write data, and means for controlling the output of the output means are provided, and when a DMA permission signal is sent from the microcomputer to the control adapter, the control means The present invention is characterized in that the output contents of the output means are made valid, the signal output from the output means is connected to the bus driver circuit as a control signal, and the gate of the bus driver circuit is controlled.

[Effect]

In the present invention, when connecting an existing control package, the address area assigned to the control package connected to the expansion unit is stored in a rewritable register at the time of system generation. When a control adapter is accessed, the comparator compares the access address with the data stored in the register, and outputs a match signal if the access address is within the address area of the control package. and controls the gates of the bus driver circuits connected to the common bus.

Note that if this access is for reading data, the gate control is passed from the expansion unit side to the basic unit side.

In addition, when connecting a control package with a DMA function, use the DM of the control adapter with a mask function during DMA.
Information indicating whether ilDMA is data reading or data writing is stored in the direction register corresponding to the number of A channels by software. When the adapter makes a DMA request, the microprocessor outputs a bus grant, which bus grant is responded to as a DMA grant signal to the adapter, which response validates the contents of the direction register; Gate control is performed by connecting the output of can be written.

C Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a common bus connection system in a first embodiment of the present invention.

The common bus connection system of this embodiment is as shown in Figure 1.
Basic unit 1. and an extension unit 2, which are connected to the connection section 16. and is connected to the common bus 10 via bus driver circuits 11-14.

The basic unit 1 includes a microcomputer 3° control package 5, 6 . and a bus control circuit 4, and the bus control circuit 4 outputs a bus control signal 15. Further, the expansion unit 2 includes III control packages 7 to 9.

FIG. 2 is a configuration diagram of a bus control circuit in the common spring connection system according to the first embodiment of the present invention (see FIG. 1).
.

The bus control circuit 4 of this embodiment includes registers 17-19 and comparators 20-22.

Registers 17-19 store address areas assigned to packages 7-9 connected to expansion unit 2, respectively. In the case of storing data 23, the data 23 is stored using the control signal 24.

Further, comparators 20 to 22 are connected to registers 17 to 19.
, the stored data 26 to 28 are compared with the address 23 when accessing the control packages 5 to 9, and if they match, match signals 29 to 3 are output, respectively.
Outputs 1.

The match signals 29 to 31 thus output are ORed, and further ANDed with the read signal 32 and outputted as the bus control signal 15.

FIG. 5 is an operation flowchart of the common bus connection system in the first embodiment of the present invention.

As shown in FIGS. 1 and 2, control packages 5 to 9
(500), the address 25 is transferred to registers 17-1 by comparators 20-22.
9 is compared with the stored data 26 to 28 (501).

If any of these addresses match, (5
02), one of the coincidence signals 29 to 31 is output (5
03), furthermore, the bus control signal 15 is output (50
4). This bus control signal 15 is.

Bus driver circuit 1 connected to this bus control signal 15
Gates 1 to 12 are opened and access is performed (505).

According to this embodiment, by rewriting the data stored in the registers 17 to 19 during system generation, the control packages 5 and 6 connected to the basic unit 1 can be
．． Also, since the addresses of the control packages 7 to 9 connected to the expansion unit 2 can be arbitrarily assigned, the basic unit 1. Also, mounting of the package in the expansion unit 2 becomes easy.

FIG. 3 is a configuration diagram of a common bus connection system in a second embodiment of the present invention.

The common bus connection system of this embodiment consists of basic units 1.
and expansion unit 2, which are connected to connector 45.
．． and is connected to the common bus 42 via bus driver circuits 43 and 44.

The basic unit 1 includes a microcomputer 3, a main memory 64. Control package 65. DMA controller 66.
67 and the bus driver control section 68. The expansion unit 2 includes control packages 60, 61, 69,
These are connected to a common bus 42, which includes:
It is connected to the connector 45 through bus driver circuits 43, 44, and further connected to the basic unit 1 by a cable. Also, DMA from microcomputer 3
The permission signal 53 is also transmitted through this common bus 42. and via cables to the control package 60.61°69.

The control package 65 serves as a mask during DMA, and
The A controller 66 receives the DMA request signal 52 from the control package 65 and the like.

It is connected to the microcomputer 3 and connected to the bus request permission signal 46 from the microcomputer 3. This bus permission signal 46 is responded to as a DMA permission signal 53 to the control package 65 and the like.

Similarly, the DMA controller 67 connects DMA requests from the control packages 60, 61, and 69 of the expansion unit 2 to the microcomputer 3.

The bus driver control unit 68 receives the register write signal 50.
is connected to the common bus 42 by a bus driver signal 47
is output and connected to bus driver circuits 43 and 44 by this bus driver signal 47.

FIG. 4 is a block diagram of the bus driver control section 68 in the common bus connection system according to the second embodiment of the present invention.

The bus driver control section 68 of this embodiment includes flip-flops 56. AND gate 57. and an OR gate 59.

The flip-flop 55 is a rewritable direction register, and is provided in correspondence with the number of DMA channels that the bus control system has. This direction register 55 includes DMA
Control packages 60, 61, 65.6 that sometimes act as masks
Information indicating whether the DMA operation of 9 is data reading or data writing is data 50. and register write signal 54. The output of the direction register 55 is ANDed with the DMA permission signal 49, and the output of the direction register 55 is ANDed with the DMA permission signal 49.
When it becomes active, it becomes valid and the control signal 58 is output. This control signal 58 is logically summed by an OR gate 59 and outputted as a bus driver control signal 47.

Note that this direction register 55. and AND gate 57
The circuit consisting of the DMA that the bus control system has
Since it is necessary to provide the same number of circuits as the number of channels, four circuits are provided in this embodiment. In addition, a DMA request signal 52 and a DMA permission signal 53 in the basic unit l,
DMA permission signal 48 in expansion unit 2. and D.M.A.
There are four permission signals 49 each.

FIG. 6 is an operation flowchart of the common bus connection system in the second embodiment of the present invention.

For example, for DMA in which the control package 69 is the master, as shown in FIGS. 3 and 4.

When the direction information of the control package 69 is stored in the direction register 55 and the DMA start condition is satisfied, the control package 69 outputs the DMA request signal 48 (600). This DMA request signal 48 is transmitted to the DMA controller 67, and the DMA controller 67 outputs the bus request signal 46 to the microcomputer 3 (601).

The microcomputer 3 releases the bus and outputs the bus permission signal 46 to the DMA controller 67 (602).
.

The DMA controller 67 receives the bus permission signal 46,
A DMA permission signal 49 is output to the control adapter of the control package 69 and the bus driver control unit 68 (60
3).

The DMA permission signal 49 enables the bus driver control unit 68 to enable the AND gate connected to the direction register 55 corresponding to the DMA channel of the control adapter, outputs the information in the direction register 55, and outputs the bus driver control signal. 47 is output (604).

The control adapter receives the DMA permission signal 49 and sends the DM
A operation is performed (605). If the operation is data writing, the direction register 55 in the bus driver control unit 68 stores information that makes the AND gate 57 active, so the bus driver control signal 47 becomes active and the bus driver circuit 44 Once enabled, the write data is sent to the expansion unit 2 via the common bus.
The data is sent to the baseboard unit 1 side and written into the main memory 64. Further, in the case of a data read operation, the bus driver signal 47 becomes inactive and the bus driver circuit 43 becomes effective.

The read data is sent from the basic unit 1 side to the expansion unit 2 side via the common bus 42.

In addition, the control packages 60° and 6 of the expansion unit 2
1 becomes the master and performs DMA, the same operation is performed, and the DMA operation in which the control backup cage 65 of the basic package 1 is a mask is performed using the DMA request redemption code 52. DM
Since this is done using the A controller 66° and the DMA permission signal 53, there is no need to use the bus driver circuits 43, 44.

According to this embodiment, the control packages 60, 61 and 65, 69 having the mask function during DMA are the basic unit 1.
．． and the expansion unit 2 can be easily implemented.

〔Effect of the invention〕

According to the present invention, an existing control package can be used as a basic unit.
It can be easily installed in both the control package and the expansion unit, ensuring compatibility of control packages. Also, D
A control package that serves as a mask during MA can also be implemented in the same way.

In this way, it is possible to arbitrarily configure a system that maintains compatibility.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a common bus connection system according to the first embodiment of the present invention, FIG. 2 is a block diagram of a bus control circuit in the common bus connection system according to the first embodiment of the present invention, and FIG.
FIG. 4 is a configuration diagram of a common bus connection system according to a second embodiment of the present invention, FIG. 4 is a configuration diagram of a bus driver control section in a common bus connection system according to a second embodiment of the present invention, and FIG. FIG. 6 is an operation flowchart of the common bus connection system in the first embodiment of the invention. FIG. 6 is an operation flowchart of the common bus connection system in the second embodiment of the invention. 1: Jl, main unit, 2: ill unit, 3: microcomputer, 4: bus control circuit, 5 to 9: control package, 10: common bus, 11 to I4: bus driver circuit, 15: bus control signal, 16 = connection part. 17-19: Register, 20-22: Converter, 2
3: Data signal (address), 24: Control signal. 25 Near address, 26-28: Stored data, 29-31
D Match signal, 32: Read signal, 60, 61° 65.
69: Control package, 64: Main memory. 66.67: DMA controller, 68: Bus driver control unit, 42: Common bus, 43, 44: Bus driver circuit, 45: Connector, 46: Bus request signal (bus permission signal), 47: Bus driver control signal. 48.52: DMA request signal, 49.53: DMA permission signal, 54: Register write signal, 55: Flip-flop (direction register), 56: Direction register output, 5
7: AND gate, 58: Control signal, 59: OR gate. Figure 1 Figure 2 Figure 4 Figure 5 Bus control system Figure 6 Bus control system

Claims (1)

[Claims] 1. A microcomputer, etc. is housed in the basic unit,
and a common bus connection system in which a common bus connection with an extension unit accommodating a control package is made via a bus driver circuit, comprising means for storing an address area assigned to a control package accommodated in the extension unit; The number of means for comparing the address area stored in the storage means and the address of the control package at the time of access is provided in the same number as the number of slots in the expansion unit, and the address area stored in the storage means and the address at the time of access of the control package are provided. and the address at the time of access by the comparing means,
If the address at the time of access is within the address area, the common bus outputs a control signal, connects the control signal to the bus driver circuit, and performs gate control of the bus driver circuit. Connection method.