JPS635566A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS635566A JPS635566A JP15034486A JP15034486A JPS635566A JP S635566 A JPS635566 A JP S635566A JP 15034486 A JP15034486 A JP 15034486A JP 15034486 A JP15034486 A JP 15034486A JP S635566 A JPS635566 A JP S635566A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- high melting
- polycrystalline silicon
- semiconductor substrate
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000002844 melting Methods 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000008018 melting Effects 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 239000000126 substance Substances 0.000 claims abstract 2
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 7
- 239000010936 titanium Substances 0.000 abstract description 7
- 229910052719 titanium Inorganic materials 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 5
- 239000007789 gas Substances 0.000 abstract description 4
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 2
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 239000008188 pellet Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に高融点金属
シリサイド層の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a high melting point metal silicide layer.
従来の高融点金属シリサイド層の形成方法の一例を第２
図（ａ）〜（ｅ）にて説明する。An example of the conventional method for forming a high melting point metal silicide layer is shown in the second example.
This will be explained with reference to Figures (a) to (e).
まず、第２図（ａ）に示すように、半導体基板１に拡散
層２とゲート絶縁膜３、多結晶シリコンからなるゲート
電極４を形成する。First, as shown in FIG. 2(a), a diffusion layer 2, a gate insulating film 3, and a gate electrode 4 made of polycrystalline silicon are formed on a semiconductor substrate 1.
次に、第２図（ｂ）に示すように、絶縁膜５、たとえば
化学気相成長法による酸化膜を被着する。Next, as shown in FIG. 2(b), an insulating film 5, such as an oxide film formed by chemical vapor deposition, is deposited.
その後、第２図（Ｃ）に示すように、異方性ドライエッ
チング（以下ＲＩＥという）法により絶縁膜５を除去し
拡散層２と多結晶シリコン４の表面を露出させる。この
とき多結晶シリコン４の側面には酸化膜５が残るが基板
あるいは多結晶シリコン中にＲＩＥに用るガスからの不
純物６たとえば炭素、フッ素、塩素などが混入する０次
に、第２図（ｄ）に示すように高融点金属７、例えばチ
タンを被着する。次いで、第２図（ｅ）に示すように、
熱処理により高融点金属と半導体基板あるいは多結晶シ
リコンとを反応させ、高融点金属シリサイド層（チタン
シリサイド）８を形成し、未反応の高融点金属を除去し
ていた。Thereafter, as shown in FIG. 2C, the insulating film 5 is removed by anisotropic dry etching (hereinafter referred to as RIE) to expose the surfaces of the diffusion layer 2 and polycrystalline silicon 4. At this time, an oxide film 5 remains on the side surface of the polycrystalline silicon 4, but impurities 6 such as carbon, fluorine, chlorine, etc. from the gas used for RIE are mixed into the substrate or polycrystalline silicon. As shown in d), a high melting point metal 7, for example titanium, is deposited. Next, as shown in FIG. 2(e),
The high melting point metal is reacted with the semiconductor substrate or polycrystalline silicon by heat treatment to form a high melting point metal silicide layer (titanium silicide) 8, and the unreacted high melting point metal is removed.
゛ 〔発明が解決しようとする問題点〕上述した従来
の高融点金属シリサイド層の形成方法は、ＲＩＥ法によ
り絶縁膜を除去したときにエツチングガスからの不純物
が半導体基板あるいは多結晶シリコン中に混入している
ため、その後高融点金属と半導体基板あるいは多結晶シ
リコンと熱反応させ高融点金属シリサイド層を形成して
も、不均一で層抵抗の高い高融点金属シリサイド層にな
っていた。゛ [Problems to be solved by the invention] In the conventional method for forming a high-melting point metal silicide layer described above, impurities from the etching gas get mixed into the semiconductor substrate or polycrystalline silicon when the insulating film is removed by the RIE method. Therefore, even if a refractory metal silicide layer is formed by thermally reacting the refractory metal with a semiconductor substrate or polycrystalline silicon, the resulting refractory metal silicide layer is non-uniform and has a high layer resistance.
本発明の目的は、従来の欠点を除去し、均一で低抵抗な
高融点金属シリサイド層を得ることができる半導体装置
の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the conventional drawbacks and obtain a uniform, low-resistance, high-melting-point metal silicide layer.
本発明の半導体装置の製法方法は半導体基板の主表面側
に高融点金属シリサイド層を有する半導体装置の製造方
法において、前記半導体基板表面あるいは前記半導体基
板上の多結晶シリコン表面に絶縁膜を形成する工程と、
異方性ドライエツチング方により前記絶縁膜を除去し高
融点シリサイド層を形成する前記半導体基板あるいは基
板上の多結晶シリコン表面を露出させる工程と、前記半
導体基板を熱処理する工程と、前記半導体基板表面ある
いは前記多結晶シリコン表面に高融点金属を被着させ熱
処理により高融点金属シリサイド層を形成する工程とを
含んで構成される。A method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device having a high melting point metal silicide layer on the main surface side of a semiconductor substrate, which includes forming an insulating film on the surface of the semiconductor substrate or the surface of polycrystalline silicon on the semiconductor substrate. process and
a step of removing the insulating film by an anisotropic dry etching method to expose the semiconductor substrate to form a high melting point silicide layer or a polycrystalline silicon surface on the substrate; a step of heat-treating the semiconductor substrate; and a step of heat-treating the semiconductor substrate surface. Alternatively, the method may include a step of depositing a high melting point metal on the surface of the polycrystalline silicon and forming a high melting point metal silicide layer by heat treatment.
次に、本発明の実施例について図面を参照して説明する
。第１図（ａ）〜（ｃ）は本発明の一実施例を説明する
ために工程順に示したペレットの縦断面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(c) are vertical cross-sectional views of pellets shown in order of process for explaining one embodiment of the present invention.
まず、第１図（ａ）に示すように、拡散層２．ゲート酸
化膜３．多結晶シリコン４を形成した表面に化学気相成
長法により酸化膜を形成した後異方性エツチングにより
露出した後、窒素雰囲気中で９００℃、３０分の熱処理
を行なう。この熱処理によりエツチングガスにより混入
された不純物が外拡散する。First, as shown in FIG. 1(a), a diffusion layer 2. Gate oxide film 3. An oxide film is formed on the surface on which polycrystalline silicon 4 is formed by chemical vapor deposition, and after being exposed by anisotropic etching, heat treatment is performed at 900° C. for 30 minutes in a nitrogen atmosphere. Through this heat treatment, impurities mixed in by the etching gas are diffused out.
次に、第１図（ｂ）に示すように、高融点金属であるチ
タン７をスパッタリング法により被着する。Next, as shown in FIG. 1(b), titanium 7, which is a high melting point metal, is deposited by sputtering.
次に、第１図（Ｃ）に示すように、チタンと半導体基板
、多結晶シリコンとを熱反応させ、高融点金属シリサイ
ド層であるチタンシリサイド層１８を形成し、未反応の
チタンを除去する。Next, as shown in FIG. 1C, titanium, the semiconductor substrate, and polycrystalline silicon are thermally reacted to form a titanium silicide layer 18, which is a high-melting point metal silicide layer, and unreacted titanium is removed. .
以上説明したように本発明は、絶縁膜をＲＩＥ法により
除去した後、熱処理を行なうことにより、半導体基板あ
るいは多結晶シリコン中に混入した不純物を外拡散させ
た後、高融点金属と反応させ高融点金属シリサイド層を
形成するため均一で、低抵抗な高融点金属シリサイド層
を得ることができる。As explained above, in the present invention, after an insulating film is removed by the RIE method, impurities mixed in a semiconductor substrate or polycrystalline silicon are diffused out by heat treatment, and then reacted with a high melting point metal to increase the Since a melting point metal silicide layer is formed, a uniform, low resistance high melting point metal silicide layer can be obtained.
第１図（ａ）〜（Ｃ）は本発明の一実施例を説明するた
めに工程順に示したベレットの縦断面図、第２図（ａ）
〜（ｅ）は従来の半導体装置の製造方法の一例を説明す
るために工程順に示した縦断面図である。
１・・・半導体基板、２・・・拡散層、３・・・ゲート
絶縁膜、４・・・多結晶シリコン、５・・化学気相成長
法による酸化膜、６・・・エツチングにより混入した不
純物、７・・・チタン、８，１８・・・チタンシリサイ
ド層。
茅 ！ 凹
第 ２ 回FIGS. 1(a) to (C) are longitudinal cross-sectional views of a pellet shown in order of steps to explain one embodiment of the present invention, and FIG. 2(a)
-(e) are vertical cross-sectional views shown in order of steps to explain an example of a conventional method for manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Diffusion layer, 3... Gate insulating film, 4... Polycrystalline silicon, 5... Oxide film by chemical vapor deposition method, 6... Mixed by etching Impurity, 7...Titanium, 8,18...Titanium silicide layer. Kaya! concave 2nd
Claims (3)
を有する半導体装置の製造方法において、前記半導体基
板表面あるいは前記半導体基板上の多結晶シリコン表面
に絶縁膜を形成する工程と、異方性ドライエッチング法
により前記絶縁膜を除去し高融点金属シリサイド層を形
成する前記半導体基板あるいは基板上の多結晶シリコン
表面を露出させる工程と、前記半導体基板を熱処理する
工程と、前記半導体基板表面あるいは前記多結晶シリコ
ン表面に高融点金属を被着させ熱処理により高融点金属
シリサイド層を形成する工程とを含むことを特徴とする
半導体装置の製造方法。(1) In a method of manufacturing a semiconductor device having a high melting point metal silicide layer on the main surface side of a semiconductor substrate, the step of forming an insulating film on the surface of the semiconductor substrate or the surface of polycrystalline silicon on the semiconductor substrate; a step of removing the insulating film by a dry etching method to expose the semiconductor substrate or the polycrystalline silicon surface on the substrate to form a high melting point metal silicide layer; a step of heat-treating the semiconductor substrate; 1. A method for manufacturing a semiconductor device, comprising the steps of depositing a high melting point metal on a polycrystalline silicon surface and forming a high melting point metal silicide layer by heat treatment.
求の範囲第（１）項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim (1), wherein the atmosphere in which the heat treatment is performed is an inert atmosphere.
は多結晶シリコン上に薄い酸化膜を形成した後前記薄い
酸化膜をケミカルウェットエッチング法により除去する
特許請求の範囲第（１）項記載の半導体装置の製造方法
。(3) The semiconductor device according to claim (1), wherein the heat treatment is performed in an oxygen atmosphere to form a thin oxide film on the semiconductor substrate or polycrystalline silicon, and then the thin oxide film is removed by chemical wet etching. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15034486A JPS635566A (en) | 1986-06-25 | 1986-06-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15034486A JPS635566A (en) | 1986-06-25 | 1986-06-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS635566A true JPS635566A (en) | 1988-01-11 |
Family
ID=15494940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15034486A Pending JPS635566A (en) | 1986-06-25 | 1986-06-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS635566A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58154270A (en) * | 1982-03-09 | 1983-09-13 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5961182A (en) * | 1982-09-30 | 1984-04-07 | Toshiba Corp | Manufacture of semiconductor device |
-
1986
- 1986-06-25 JP JP15034486A patent/JPS635566A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58154270A (en) * | 1982-03-09 | 1983-09-13 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5961182A (en) * | 1982-09-30 | 1984-04-07 | Toshiba Corp | Manufacture of semiconductor device |
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