JPS635573A - Manufacture of junction type fieldeffect transistor - Google Patents

Abstract

PURPOSE:To make it possible to form a gate electrode in an impurity diffusion region in the manner of self-alignment, by coating a metallic film for a gate electrode after providing a third dielectric film with eaves utilizing the speed difference of a chemical etching. CONSTITUTION:An N-type IN0.53Ga0.47As layer 12 is grown an a semi-insulative InP substrate 11 by a epitaxial method. A first dielectric film 13, a second dielectric film 14 and a third dielectric film 15 composed of the same material as the first dielectric film 13 are coated in order. Then an aperture for diffusion of P-type impurity is arranged by a RIE method, and Cd is diffused. The second dielectric film 14 at the aperture part for impurity diffusion is subjected to a undercut to arrange eaves of the third dielectric film 15, and then a metallic film 17 composed of AuZn, etc. for a gate electrode is coated on the surface of a P-type region 16 in the manner of self-alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a high-speed junction field effect transistor used in a frequency band of several 100 Mb/s to Gb/a.

[Conventional technology]

A method for manufacturing a conventionally manufactured n-junction field effect transistor (hereinafter abbreviated as J@FET) is shown in Fig. 2 (
There are nine things shown in ω~(C) ("Technical Digest IOC '83 Talkie w
(Technical Digest 100C'
83(Tokyo) J, 28B4-3, 18
6 (1983)). The manufacturing method of this JFET is
In@4sGao, 4yAa t-channel layer and the following: 1) D1 (as shown in Figure 2), semi-insulating In
n-type In64s Gacb4yAsJ on P substrate 11
After forming 112k, as shown in FIG. 2(c), a dielectric film 20t is formed, and a P-type region 16 is formed as a diffusion mask f'Lt1''.Next, as shown in FIG. 2(c), a dielectric film 20t is formed. In addition, a gate electrode 2 is formed on the P-type region 16, and a source electrode 22 and a drain electrode 27t are further provided.

[Problem that the invention seeks to solve]

- Generally, metal placement on the gate stripe of a J-FET is
- It is important to suppress the increase in thermal noise. The equivalent input noise current (in'') of this J-FET is given by the following equation.

Here, k is the Boltzmann constant, T is the absolute temperature, Δf is the frequency band, C1 is the input capacitance, gm is the mutual conductance, and α is the noise constant n expressed by the following equation.

a=αg+gm・Rg ・・・・−・ (Riko’s (
In formula 2), C0 is a constant and takes a value of 0.7 to 1.

Ma2. Rg is the series resistance of the gate stripe and is expressed by the following equation.

] W Rg= Pts ・・・・・・・・・(
3) L In this equation (3), W and L are the gate width and gate length, respectively, and P8 is the sheet resistance of the gate. If the gate is formed only by diffusion, ptt=2 and Ω/
It becomes m q.

If W=300μm, L=1μm, Rg=86Ω
When 5 s gm = 10 ms, the value of the second term on the right side of equation (2) is 860, so the value of 1 is C61
It's bigger than 1C! 7. Thermal noise of J-PET increases significantly.

Therefore, applying a metal film ls on the gate is an important point when trying to reduce noise. It is extremely difficult to perform the gate arrangement Mk in the impurity diffusion region using the elaborate steps (a) to (C), as it requires precise alignment.

An object of the present invention is to solve such problems and to form a J@ that can not only form an electrode in a self-aligned manner on the gate, but also form source and drain electrodes in a self-aligned manner.
[Means for solving the problems] The J@FET0 lining method of the present invention provides a method for manufacturing an FET, which includes a first dielectric film on the surface of the first dielectric film, and a first dielectric film on the surface of the first dielectric film. a second dielectric film having a higher chemical etching rate and an equivalent reactive ion etching (hereinafter abbreviated as RIE) rate than the first dielectric film; and a third dielectric film made of the same material as the first dielectric film. A first step of sequentially depositing dielectric films, and masking the critical photoresist on the third dielectric film and applying RIEK only to the third, second, and first dielectric films. a second step of selectively removing the first photoresist to form an opening, a step of jg3 in which impurities are completely diffused into the semiconductor surface through the seven openings after removing the first photoresist, and a step of chemical etching. Step 4 of undercutting the second dielectric film in the opening, and applying a gate only to the opening in a self-aligned manner by utilizing the entire area of the third dielectric film caused by the undercut. 'jg5 step of forming an IE electrode, a sixth step of applying a thick second photoresist to fill the opening and obtaining a flat surface, and applying an etchant to the third dielectric material for WR elementary plasma treatment. a seventh step of removing the above-mentioned 7-odd resist until the gate electrode metal film deposited on the film is exposed; an eighth step of removing the exposed gate electrode metal film by chemical etching; After removing the third and second dielectric films by chemical etching, chemical etching is continued to remove this second dielectric film.
a ninth step of etching the first dielectric film by using the second photoresist as a whole mask to fill the undercut portion of the dielectric film; A tenth step of forming source and drain electrodes in a self-aligned manner using the film and the second seven-layer resistor (1).

[Effect]

In the present invention, the first and third dielectric films have a low chemical etching rate, and the first and third dielectric films have a high chemical etching rate.
The RIB speed is almost the same as that of the first and third dielectric films.
A t3-layer film obtained by sequentially laminating a dielectric film is subjected to reactive ion etching (RIE) to perform impurity diffusion to form a gate region, and then the difference in chemical etching speed is Since the metal film for the gate electrode and the like is entirely deposited after the third dielectric film is provided with a metal layer using the third dielectric film, the gate electrode can be formed in a self-aligned manner in the impurity diffusion region. 9. After that, the opening is filled with a thick photoresist and the surface is smoothed, and then the photoresist is removed by oxygen plasma treatment until the third dielectric film is exposed, and then chemical etching is performed. The metal film for the gate electrode on the third dielectric film and the third and lx2 dielectric films are removed using a method of removing the gate electrode metal film and the third and lx2 dielectric films.
Since the metal film for the source and drain electrodes is attached after chemically etching the first dielectric film using photoresist as a mask, it is possible to form the metal film on the source and drain/electrodes in a self-aligned manner. . This eliminates the need for severe alignment work associated with the conventional method, making it possible to significantly improve manufacturing yield.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

Nos. 111(a) to 111(g) are cross-sectional views of nine elements showing one embodiment of the present invention in the order of steps.
This figure shows a method for manufacturing a J-FET using an 8-layer hoArA channel.

First, as shown in FIG. 1(a), a semi-insulating InP substrate 11 is
An n-type In@5sGaa47As layer 12t-epitaxially grown on top. At this time, the layer thickness is 2 μm, and the carrier concentration is about n~5×10 cIN.
), the n-type Intss Gaat? As
A first dielectric film 13 with a thickness of about 0.2 μm, a second dielectric film 14 with a thickness of about 0.2 μm, and a first dielectric film 13 with a thickness of about 0.2 μm are formed on the surface of the N 12. A third dielectric film 15't made of the same material is sequentially deposited, then an opening gold film for RIEK process 5P type impurity diffusion is applied as a photoresist mask, followed by a photoresist) Cds Pg source gold after Th removal. At this time, the Pn junction depth is approximately 1 μm. Note that the first and third dielectric films 13 and 15 are SiN films, and the second dielectric film is a Si film.
It is also possible to continuously improve the plasma CVD method (heating at 300° C.). At this time, the etching rate of the 5 lot film with respect to aqueous solutions of HF and NH4F (buffered acid) was about one order of magnitude higher than that of the SiN film.
The nine RIE speeds using Fa gas are approximately equal. Maft C
Depending on F a gas, n-type Inoss Gae4yAs
Layer 12 is hardly etched. tx Here, Cd for impurity diffusion? Although all the examples used here are nine, it is also possible to use Zntl-.

Next, as shown in FIG. 1(C), an undercut of about 2 μm is made in the second dielectric film 14 at the opening for impurity diffusion by etching with buffered acid. After forming the area around the body film 15, a gate electrode metal film 17t made of AuZn or the like is deposited on the surface of the P-type region 16 in a self-aligned manner.

At this time, the gate electrode metal film 17 is attached to the third dielectric film 15.
As shown in Figure 1(d), the zero-order particles also adhere to the surface of
After coating the first photoresist film with a thickness of 3 to 5 μs, fill in the opening and flatten the surface.

Next, in FIG. 1(e), after removing the photoresist 187 deposited on the third dielectric film 15 by oxygen plasma treatment until the gate electrode metal film 17 is exposed,
A second and third dielectric film 15 is coated with a KI+ b-based etchant.
The upper metal film 17 for gate electrode is removed. Next, Figure 1 (
In f), after removing the third dielectric film 15 and the second dielectric film 14 in a buffered acid solution, etching is continued completely, and the second! A photoresist 18 is masked and buried in the undercut portion of the W electric film 14, and the first dielectric film 13'5 is etched to form an n-type I.
no, m s Ga4.47 A3 layer 12t - exposed. Next, in Fig. 1 ω, n-type Ino, 5sG
AuGeNi is self-aligned on the surface of the acL4yAs layer 12.
Then, a metal film 19t for electrodes is deposited on the source and drain. Finally, remove the unnecessary source and drain electrode metal 18t (photoresist in Figure 1) and lift off the unnecessary metal 19 for the source and drain electrodes, then heat treat to produce alloying. The process is completed by removing the dielectric film 13 of No. 4.

〔Effect of the invention〕

In view of the above explanation, by incorporating the present invention, it is possible to form not only the gate electrode in a self-aligned manner in the impurity diffusion region in the manufacture of J-FIT, but also the source and drain electrodes to be formed in a self-aligned manner. As far as possible, the conventional method requires
L72: MB eyelet is completely unnecessary, making it possible to significantly improve manufacturing yield.

[Brief explanation of the drawing]

FIGS. 1(&) to (6) are cross-sectional views showing an embodiment of the J-FET manufacturing method of the present invention in the order of steps, and FIGS. 2(a) to (c).
) is a cross-sectional view showing all steps in the conventional example. 11...Semi-insulating Inp substrate, 12...-
・N-type Ino, s sGa@, 4yAa layer, 13...
...first dielectric film, 14...second dielectric film, 15...jg3 dielectric film, 16...
...P-type region, 17...metal film for gate electrode,
18...Photoresist, 19-...Metal film for source and drain electrodes %20...-Dielectric film, 21-...Gate electrode, 22-... Source electrode, 23.--Dray/electrode. g yvm

Claims (1)

[Claims] a first dielectric film on a semiconductor surface; a second dielectric film having a higher chemical etching rate and an equivalent reactive ion etching rate than the first dielectric film; and the first dielectric film. a first step of sequentially depositing a third dielectric film made of the same material as the third dielectric film, and reactive ion etching using the first photoresist provided on the third dielectric film as a mask. a second step of selectively removing only the second and first dielectric films to form an opening; and after removing the first photoresist;
a third step of diffusing impurities into the semiconductor surface through the opening;
a fourth step of undercutting the second dielectric film in the opening by chemical etching; and a fourth step of undercutting the second dielectric film in the opening by chemical etching; a fifth step of forming a gate electrode only in the opening in a consistent manner; a sixth step of applying a thick second photoresist to fill the opening and obtaining a flat surface; and an oxygen plasma treatment. a seventh step of removing the second photoresist until the gate electrode metal film deposited on the third dielectric film is exposed; and removing the gate electrode metal film exposed by chemical etching. an eighth step of
After removing the second dielectric film, etching is continued to remove the first dielectric film using the second photoresist embedded in the undercut portion of the second dielectric film as a mask. a ninth step of etching; and a tenth step of forming source and drain electrodes in a self-aligned manner using the locally left first dielectric film and the photoresist. A method for manufacturing a junction field effect transistor characterized by: