JPS635647A - Synchronizing test method - Google Patents

Abstract

PURPOSE:To continue testing even if processing lags owing to the detection of fault in one or both modules in some test step and to substantialy improve operability by conducting a test by acquiring synchronization. CONSTITUTION:When a master module side reads status data '01', said data '01' is temporarily stored in a register 32, and simultaneously a status register 41 on a normal module side is reset to set its content to '00'. According to an out instruction 11, the master module side transmits a status read command packet 51, and recognizes the reception of a status data packet 52 due to interruption, after which the received status data is read according to an in instruction 12. such procedures are repeated by monitoring a test interruption command from an operator until status data '01' showing the completion of synchronization is received. Thus acquiring synchronization between modules ends in such a way.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a synchronous test method, and more particularly to a program-based module-to-module synchronous test method in a packet switching system.

Conventional technology In the past, in this type of test, after synchronization was performed by the operator at the beginning of the test, the receiving module confirmed that the expected test data was transmitted from the transmitting module within a certain period of time. After that, the receiving module becomes a transmitting module and starts transmitting test data, and the test is performed while being synchronized by sequential timing.

In such conventional synchronous test methods, tests are performed in synchronization depending on whether or not the expected test data is received each time, so if a fault is detected in either module, The problem is that synchronization is lost due to failure handling, making it impossible to continue subsequent tests, resulting in extremely poor operability.

OBJECTS OF THE INVENTION An object of the present invention is to ensure that even if a fault occurs in any module during a certain test step and the processing of the fault is delayed, synchronization will always be achieved after the test step is completed;
Therefore, it is an object of the present invention to provide a synchronous test method that allows the test to be easily continued.

Structure of the Invention According to the present invention, one of the packet switching modules interconnected via a common bus has a status information storage means for setting the status information of the own module, and the other module has the status information storage means for setting the status information of the module itself. A module-to-module synchronization test method in a packet switching system comprising reading means for reading the contents of the status information storage means of the modules, the synchronization preparation indicating the completion of synchronization premature ejaculation to the status information storage means of the first module. 1. Store completion information, and indicate that the synchronization preparation completion information has been read by the reading means in the other module.
By using iIX, a synchronous test method is obtained, which is characterized in that opposing tests are executed while establishing synchronization between modules.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a conceptual block diagram of an embodiment of the invention. In the figure, there are opposed modules for packet exchange that perform synchronous tests with each other, and these opposed modules are a master module and a general module, as clearly indicated in the figure. Each module includes a control processor 1, 2 in which a counter test program is stored, and a mask packet exchange unit 3. - general packet switching unit 4. The mask packet switching unit 3 and the general packet switching unit 4 are commonly connected by a common bus 5.
An opposing test is performed via this common bus 5.

The general packet switching unit 4 is provided with a status register 41 for storing status information of its own module, and any status data can be set by an out command 21 from the control processor 2. Further, the setting contents of this status register 41 can be read and confirmed by the IN instruction 22 from the control processor 2.

The mask packet exchange unit 3 has a command register 3.
1 is provided so that a status read command packet 51 to the general module can be sent in response to an out command 11 from the control processor 1. Further, a status register 32 for the master module is provided, and the status data 5 of the status register 41 of the general module read in response to the status read command packet 51 mentioned above is provided.
This is for temporarily storing 2. The contents of this status register 32 can be read by the IN command 12 of the control processor 1.

Note that when the status data 52 of the general module status register 41 is read by the status read command packet 51 from the master module,
By reading this reset state using the IN command 22 of the control processor 2, it is possible to know whether or not the status data has been read by the master module 1. Note that 13 indicates response reception.

FIG. 2 is a flowchart showing the operation of the blocks shown in FIG. 1, in which (A) is a flowchart of synchronization processing on the master module side, and (B) is a flowchart of synchronization processing on the general module side. - The general module side program sets synchronization status data ""01" (expressed in hexadecimal) in the status register 41 using the out instruction 21. This status data is information indicating that preparation for synchronization is complete. The status information is not limited to "01" as long as it can be distinguished from other status information.

This status data from the master module side゛°0
1'' is read, this data "01" is temporarily stored in the register 32, and at the same time, the status register 41 on the -general module side is reset and its content becomes "OO". The control processor 4 on the module side reads this register 4 by the IN instruction 22.
It constantly monitors whether the content of 1 becomes "OO" and at the same time monitors the operator's instruction to interrupt the test.

On the master module side, the status read command packet 51 is also sent by the OUT command 11, and after confirming the reception of the status data packet 52 by the interrupt, the received status data is read by the IN command 12. Status data “01” indicates preparation for completion of synchronization while monitoring test interruption instructions from the operator.
Repeat until received. In this way, synchronization between the modules is completed.

FIG. 3 is a test operation flowchart of the test program stored in each control processor. When each test program is started, FIG. 2(A).

One test step is executed by establishing mutual synchronization according to the operating procedure in (B). When each test step is completed, synchronization is performed again, and once synchronization is established, the next test step is executed. In this way, opposing tests are executed while synchronizing with each other for each test step.

As described in detail, the present invention executes tests in synchronization with each other, so that even if processing is delayed due to the detection of a fault in one or both modules at a certain test step, the test can be performed in synchronization with each other. Since synchronization is always achieved after each step is completed, the test can be continued, which has the effect of greatly improving operability compared to conventional methods.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 and FIG.
The figure is an operational flow diagram of an embodiment of the present invention. Explanation of symbols of main parts 1.2... Control processor 31.32.41... Register ) Figure 2 (A) (B)

Claims (1)

[Claims] Among the packet switching modules interconnected via a common bus, one module has a status information storage means for setting the status information of its own module, and the other module has a status information storage means for setting the status information of the first module. A module-to-module synchronization test method in a packet switching system in which reading means are respectively provided for reading, wherein synchronization preparation completion information indicating completion of synchronization preparation is stored in the status information storage means of the one module, and the other module A synchronous test method characterized in that, by confirming that the synchronization preparation completion information has been read by the reading means, a facing test is executed while establishing synchronization between mutual modules. .