JPS635744B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a camera, and particularly to a self-timer device used for self-timer photography of a camera.

Conventionally, mechanical self-timer devices using a governor have been put into practical use, but since such devices take up a considerable amount of space, in recent years, electronic self-timer devices using CR circuits or delay circuits using counters have been developed. was suggested.

However, in such an electronic self-timer device, once the self-timer operation is started after the self-timer setting lever is set, even if the setting lever is returned to the initial state in an attempt to cancel the self-timer operation, it is not possible to do so. There was a drawback that the release was not performed, and on the contrary, the shutter was released when the release operation was performed. Therefore, the conventional device is configured such that the self-timer operation can only be canceled when a separately provided self-timer canceling member, such as a battery check button, is operated and the setting lever is then returned to its initial state. However, not only is it extremely troublesome to require double operations for release, but providing a separate release member for this purpose is problematic not only in terms of space but also in terms of manufacturing costs. There is.

The present invention has been made in view of the above-mentioned matters, and when resetting the self-timer mode during the self-timer after setting the self-timer mode with the self-timer setting operation member, the self-timer setting operation member can reset the self-timer mode. If you cancel the mode setting, the self-timer will automatically stop counting.
The purpose is to provide a self-timer that returns to normal mode.

As a configuration for achieving the above object, the present invention has a self-timer mode selection means, and by setting the self-timer mode with the selection means and putting the release operating member into the operating state, the shutter is released after the self-timer time has elapsed. In a camera having a self-timer device that performs a tally reset operation, when the self-timer mode is selected by the selection means (corresponding to 22 in FIG. 1 in the embodiment), a self-mode signal is formed and the selection is made. mode signal forming means for forming a non-self mode signal when the self-timer mode is not selected by the means; and the release operation member (corresponding to 18 in FIG. 1 in the embodiment).
and a release operation signal forming means that detects the operation of the camera and generates a release operation signal, and has a plurality of different set states, and changes from the current set state to the next set state according to the self mode signal, non-self mode signal, and release operation signal. A sequence circuit that transitions to a set state and causes the camera to perform a predetermined operation in each set state, and when the circuit is in a first set state, detects the non-self mode signal and the release operation signal. When in the first set state, the set state is shifted to a third set state upon detection of the self mode signal and the release operation signal, and Transitioning from the third set state to the second set state in response to the self-timer end signal, and further transitioning to the first set state upon detection of the non-self mode signal in the third set state. A sequence set state determining circuit (embodiment, corresponding to the circuit in FIG. 5), and magnet means (embodiment, corresponding to 396 in FIG. 5) for performing a release operation upon transition to the second set state. ), and a self-timer clocking means (in the embodiment, 6 in FIG.
It corresponds to 20. ), the release operation member is operated in the first set state and the selection state of the self-timer mode is determined, the release operation is performed in the second set state, and the release operation is performed in the third set state. The self-timer operation is canceled when the self-timer mode is deselected by the selection means during the self-timer operation.

Hereinafter, the camera system of the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a six-sided view of a camera device to which a camera system according to an embodiment of the present invention is applied, in which figure a is a front view, figure b is a top view, figure c is a bottom view,
Figure d shows a right side view, figure e shows a left side view, and figure f shows a rear view.

The camera device having the configuration shown in the figure is a single-lens reflex camera equipped with a dual-priority automatic exposure control mechanism based on the TTL photometry method, and its components are arranged with particular emphasis on its operability.

This camera device has a lens device 2 which is an optical system.
It is made up of a body 4, which is a main body system, and a variety of combinations of different types of lens devices and main body systems are possible, making it possible to take a wide range of photography. It's the same.

The lens device 2 includes a distance adjustment ring 6 and an aperture adjustment ring 8, and is attached to the body 4 by a tightening ring 10. The aperture adjustment ring 8 is constructed so that the aperture value can be preset from the body 4 side with a mark 12 attached on its circumference aligned with the index 7. The lens device 2 also includes a mechanism for transmitting information regarding the maximum aperture value and the like to the body 4 side.

The body 4 is provided with a TTL photometry function that measures the brightness of subject light introduced through the lens device 2.

Further, on the top surface of the body 4, there is a winding lever 14 that works in conjunction with the film winding spool to wind up one frame of film and to charge springs for moving the mechanical parts necessary for shutter release. Be prepared. The function of this winding lever 14 is to act as a power switch for the electrical function section within the camera device, and the power is turned on by pulling it out slightly in the direction of arrow α.

18 is a shutter release button, which is arranged on the top surface of the body 4 so that it can be pressed with the index finger of the right hand when the body 4 is held with both hands, just like in conventional cameras. Various operations required after the release start. Shutter release button 1
Disposed near button 8 is a selector lever 22 configured to select various functions by rotating around button 18. This selector lever 22 is the shutter release button 1
It can be operated with the same finger used to operate body 4, that is, the index finger of the right hand holding body 4.

Now, when the selector lever 22 is rotated to the position where the mark 24 is selected, the shutter release button 18 is locked and cannot be pressed. This lock condition can also be applied when the mark 24 is selected after the shutter release button 18 is pressed down, so that the shutter speed remains at the valve position. This allows long exposure when selected. That is,
This selection of the mark 24 by the selector lever 22 is applied to obtain two functions: to prevent the shutter release button 18 from being pressed down due to erroneous operation, and to enable long-time exposure.

Also, the selector lever 22 is marked 26
AE (Automatic
−Exposure) becomes locked. Note that the lever 22 that selects the mark 26 is a shutter button.
When the release button 18 returns after being pressed down, it automatically returns to the original position.

Furthermore, when the selector lever 22 is set to the position where the mark 28 is selected, the self-timer
The state is set. In this camera device, unlike conventional cameras, the self-timer is equipped with an electrical time counting mechanism.
Under this self-timer set state,
When the shutter release button 18 is pressed, a series of operations associated with the shutter release is controlled by an electrical signal that is emitted after a predetermined period of time. Note that during the period when the self-timer is operating, a light emitting diode (LED) lamp 3 arranged on the top surface of the body 4 and hidden below when the selector lever 22 is in its original position is activated.
2 flashes to notify that the self-timer is operating. If the selector lever 22 is returned to its original position while the self-timer is operating, the self-timer setting is canceled and the shutter can then be released normally using the shutter release button 18. Furthermore, since the self-timer mechanism in this camera is not released even after the shutter release operation is performed, self-timer photography can be repeated without having to perform the self-timer setting operation again. This function, in combination with a motor drive device, enables automatic photographing at timed intervals, and is extremely useful.

That is, while aligning the selector lever 22 provided on the top surface of the camera device body 4 to the position where the mark 28 is selected, the shutter release button 18 is kept pressed and the motor drive device is attached. When shooting, the shutter release and film winding are repeated at intervals specified by the self-timer mechanism.

When the selector lever 22 is moved to a position where the mark 30 is selected, the battery is checked. If the LED lamp 32 blinks during this battery check state, it indicates that the power battery has sufficient voltage, and if it remains off, the voltage of the power battery has decreased, and the camera equipment Informs you that the electrical function cannot operate satisfactorily. Note that the selector lever 22 that has selected the position of the mark 30 is always applied with a return force toward the position of the mark 28 by the biasing force of the spring, and when the finger is released after the battery check, the selector lever 22 moves to the position of the mark 28. is returned to the position. This function can be used if you forget to return the lever 22 after checking the battery.
This is to prevent the camera device from not only not functioning properly, but also from wasting power consumption due to the blinking LED lamp 32.

34 is a dial for setting the aperture value or shutter speed in the exposure information, and the set value is displayed on the display window 36. Here, whether the amount set on the dial 34 is an aperture value or a shutter speed is specified by switching the mode changeover switch 38. In addition, mode changeover switch 3
8, the content of the numerical value displayed on the display window 36 is changed. That is, when the mode changeover switch 38 is switched to the aperture priority mode, the aperture value is displayed on the display window 36, and when the mode selection switch 38 is switched to the shutter speed priority mode, the shutter speed is displayed on the display window 36. is displayed.

40 is an ASA sensitivity setting dial for setting the ASA sensitivity of the film to be used.

FIG. 2 is a circuit diagram showing a part of the control circuit in the camera shown in FIG.

In the figure, 614 is a shutter time control register, and shutter time information TV is input to the error register. In this embodiment, the TV value is constructed with 1/8 step precision, and the 5 bits _Q0 to _Q4 of the register 614 output a digital value corresponding to the integer number of steps of the TV.

618A to 618D are select gates, 62
0 indicates a frequency dividing circuit. In addition, the frequency dividing circuit 62
0 is composed of an integrated circuit element MC14536 (manufactured by Motorola). The integrated circuit element MC14536 is a programmable timer whose block diagram is shown in FIG. This programmable timer is
Frequency division is possible up to 24 steps, and 4-bit data input from each terminal of A, B, C, and D and 8b
Based on the signal input from the terminal, the pulse signal input from the In terminal is frequency-divided and output from the DO terminal. It should be noted that the input data from the terminals A, B, C, and D are for frequency division up to 16 stages, and the input to terminal 8b is for further frequency division by 8 stages when it is "0".

In FIG. 2, a flip-flop F39 is used to divide the clock pulse and input its Q output to the In terminal of the frequency divider circuit 620. In this embodiment system, a 64KHz pulse signal is used as the clock pulse, but through this configuration, a 32KHz on/off pulse is applied to the In terminal of the frequency divider circuit 620. becomes.

This frequency dividing circuit 620 divides the 32KHz pulse mentioned above, and when the input terminals A, B, C, D inputs are all "0" and the 8b terminal input is "1", the 16KHz pulse is output from the D0 terminal. It is configured to output a signal. That is, this frequency dividing circuit 620 has a 32K
A Hz pulse signal is frequency-divided based on input data from input terminals A, B, C, and D and an input signal from terminal 8b, and output from the D and O terminals to signal line 30. Note that this frequency dividing circuit 620 includes a reset terminal R, and is reset in accordance with an input signal from a signal line 29, which will be described later.

The select gate 618A is A1 to A4.
Q1 of the shutter time control register 614 is connected to the terminal.
From Q4, the lower 4 bits of the integer part of the shutter time control data TV are input, and from B1 to
The B4 terminal is input with data to obtain a self-time of 8 seconds, that is, "1010" data, and
The CC6 signal (described later) is on the Kb terminal, and the CC6 signal is described later on the Ka terminal.
Input CC2 signal, input B1 to B by CC2 signal
4 and input A1 to A4 by CC6 signal.
do. The setting data TV in the register 614 is set using the dial 34 when shutter priority is given, and is set as a calculated value when priority is given to aperture.

That is, this select gate 618A outputs data related to the self-second time from its D1 to D4 terminals during the time of the CC2 signal, which will be described later, and outputs shutter second time control data TV from its D1 to D4 terminals during the time of the CC6 signal.
Output from D4 terminal.

In addition, the select gate 618 is A1 to A4.
Fixed data for specifying the time of CC3 and CC4 signals, which will be described later, is input to the terminal, and B1 to
Fixed data for specifying a certain time is input to the B4 terminal as the time of the CC5 signal, which will be described later. Note that 2 msec is used as the time for these CC3 and CC4 signals, so the above
“0110” data is input to terminals A1 to A4.

Further, as the time of the CC5 signal, a time of 30 msec is used in consideration of the operating time of the AE control member, etc., and therefore "1010" data is input to the B1 to B4 terminals.

Note that this select gate 618B is connected to Ka
Through the OR gate OR57 to the terminal, CC1,
It receives the CC3 signal input and selects the A1 to A4 terminals, and the Kb terminal receives the CC5 signal input and selects the A1 to A4 terminals.
B4 terminal is selected. In other words, this select
Gate 618B outputs data related to 2 msec of time to D1 to D4 during the CC1 and CC3 signals.
Output from the terminal, CC5 signal time is 30msec
It outputs time-related data from its D1 to D4 terminals.

In addition, the select gate 618C is the A1
~A4 terminal of the select gate 618A
The D1 to D4 outputs are input to the B1 to B4 terminals, and the D1 to D4 outputs of the select gate 618B are input to the B1 to B4 terminals, and the OR gate OR55 is input to the Ka terminal.
input the CC2 signal and CC6 signal to select the A1 to A4 terminals, and also input the OR gate to the Kb terminal.
56, through OR57, CC1 signal, CC3 signal,
CC5 signal is input and B1 to B4 terminals are selected.

That is, this select gate 618C is
During the CC2 and CC6 signal times, the D1 to D4 terminal outputs of the select gate 618A are
During the CC1, CC3, and CC5 signal times, the D1 to D4 terminal outputs of the select gate 618B are output from the D1 to D4 terminals.

In addition, the select gate 618D is the A1
~ Connect the select gate 618C to the A4 terminal.
Data for creating a 2Hz signal, ie, "1101" data, is input to the D1 to D4 outputs and the B1 to B4 terminals. Also, the Ka terminal has OR gates OR54, OR55, OR56, OR5.
CC1, CC2, CC3, CC5, CC6 signals are input through 7, A1 to A4 terminals are selected, and Kb
The above-mentioned Ka is connected to the terminal through the inverter INV47.
An inverted signal of the terminal input is input, and terminals B1 to B4 are selected.

That is, this select gate 618D is
During the times of each signal CC1, CC2, CC3, CC5, and CC6, the D1 to D4 terminal outputs of the select gate 618C are output from the D1 to D4 terminals, and at times other than the above, that is, CC0, At the time of each signal CC4 and CC7, the data regarding the 2Hz signal is stored.
It is output from the D1 to D4 terminals.

The outputs D1 to D4 of the select gate 618D are input to terminals A to D of the frequency dividing circuit 620, respectively.

On the other hand, the shutter time control register 614
Q0 terminal output, i.e. shutter time control data TV
The most significant bit of
It is input to the D terminal of the frequency dividing circuit 620 through INV45 and OR gate OR53.

Further, the output of the NAND gate NAND29 is inputted to the 8b terminal of the frequency dividing circuit 620 through the AND gate AND91 which inputs the CC2 signal through the inverter INV46.

In the configuration as described above, the A to D inputs of the frequency divider circuit 620 and
The state of the 8b terminal input will be explained.

During the time of the CC0, CC4, and CC7 signals, the Kb terminal input of the select gate 618D becomes "1" and the 8b terminal input of the frequency divider circuit 620 becomes "1", so the frequency divider circuit 620's Kb terminal input becomes "1". A, B, C,
Each input terminal of D and each input of terminal 8b become "1", "0", "1", "1", "1", respectively, and therefore 16KHz is output from the D and O terminals of this frequency dividing circuit 620.
A pulse output is obtained by frequency-dividing the pulse by "1101" steps, that is, a 2 Hz pulse output.

During the time of the CC2 signal, the B1 to B4 terminal inputs of the select gate 618A are input to the A, B, C, and D terminals of the frequency divider circuit 620 through the select gates 618C and 618D, and the 8b terminal input is , "0", so A, B, of the frequency dividing circuit 620
Each input terminal of C and D and each input of terminal 8b become "0", "1", "0", "1", "0", respectively.
Therefore, the signal line 3 is connected from the DO terminal of this frequency dividing circuit 620.
For 0, a pulse output is obtained by dividing the 16KHz pulse by "1010" steps plus 8 steps, that is, a pulse output with a period of 16 seconds.

Note that this 16-second period pulse is used as the end of the self-timer time at the time when this pulse first rises from "0" to "1", that is, when 8 seconds have passed after the start of frequency division. ing.

Next, during the time of the CC3 and CC1 signals, the A1 to A4 terminal inputs of the select gate 618B are
It is input to the A, B, C, and D terminals of the frequency divider circuit 620 through the select gates 618C and 618D,
Also, since the 8b terminal input of the frequency dividing circuit 620 becomes "1", each input terminal of the A, B, C, D and 8b terminal of the frequency dividing circuit 620 becomes "0", respectively.
"1", "1", "0", "1", and therefore, from the D0 terminal of this frequency dividing circuit 620 to the signal line 30, a pulse output obtained by dividing the 16KHz pulse by "0110" steps, That is, a pulse output with a period of 4 msec is performed. In addition, this pulse with a period of 4 msec is
The time when this pulse first rises from "0" to "1", that is, the time when 2 msec has elapsed after the start of frequency division, is used as the end time of the CC3 or CC1 signal.

During the time of the CC5 signal, the B1 to B4 terminal inputs of the select gate 618B are input to the A, B, C, and D terminals of the frequency divider circuit 620 through the select gates 618C and 618D.
Since the 8b terminal input of the frequency dividing circuit 620 becomes "1", the A, B, C, D input terminals and the 8b terminal input of the frequency dividing circuit 620 become "0", "1", "0", ", respectively. 1”
,
Therefore, D0 of this frequency dividing circuit 620 becomes “1”.
From the terminal to the signal line 30, the pulse output is a 16KHz pulse divided by 1010 steps, that is, 64msec.
A periodic pulse output will be made. Note that this pulse with a period of 64 msec occurs at the time when this pulse first rises from "0" to "1", that is, after the start of frequency division.
The time when 32 msec has elapsed is used as the end time of the CC5 signal.

At the time of the CC6 signal, the A1 to A4 terminal input of the select gate 618A, that is, the shutter time control data TV, is input to the select gate 618C,
618D, the frequency divider circuit 620 A, B,
It is input to the C and D terminals, and the most significant bit of the integer part of the shutter time control data TV is “0”.
When , the 8b terminal input of the frequency divider circuit 620 is “1”
When the most significant bit of the integer part of the shutter time control data TV is "1", the frequency dividing circuit 6
The D terminal input of 20 becomes "1", and the 8b terminal input becomes "0".

Therefore, a pulse signal obtained by frequency-dividing a 16 KHz pulse signal based on the shutter time control data TV is output from the D0 terminal of the frequency dividing circuit 620 to the signal line 30.

FIG. 4 is a partial circuit diagram constituting the control circuit of the camera of the present invention together with the circuit section shown in the second figure and the circuit section shown in the fifth figure described later, and 626 is a circuit diagram 614 shown in the second figure.
628 is a shutter speed control register into which the shutter speed information TV is input, and 628 is an aperture stage number control register into which information on the number of stages of the control aperture determined by calculation or set by the dial 34 is inputted.
32 is a data selector, and 642 is a down counter.

The data selector 632 has the Q0 to Q7 terminal outputs of the narrowing down control register 628 inputted to its B7 to B0 terminals, and also inputs the Q5 to Q7 terminal outputs of the shutter seconds control register 626, that is, the shutter seconds control data TV. The decimal information of 3 bits below the decimal point is input to the A2 to A0 terminals.
Further, this data selector 632 has a "1" signal input to its A3 terminal, and its A4 to A7 terminals are grounded. This data selector 632 also has CC4 on its terminal Ka and CC4 on its terminal Kb.
The CC3 signal is input, and therefore, during CC3 time, this data selector 632 outputs the narrowing down stage number control data AVs from its D0 to D7 terminals.
At CC4 time, this data selector 632
will output the decimal point information of the shutter time control data from its D0 to D7 terminals.

The D0 to D7 outputs of this data selector 632 are input to J0 to J7 of the down counter 642, and are input to the PRE terminal via the OR gate OR59.
When the CC3 signal or CC4 signal is input,
The down counter 642 takes in and stores the output data of the D0 to D7 terminals of the data selector 632.

Incidentally, this down counter 642 uses the above-mentioned J0 to J7 based on its clock terminal CLK input.
The data input and stored from the terminal is subtracted and counted, and if a carry (borrow) occurs as a result, a signal indicating this is output from the CO2 terminal. This CO terminal output signal is normally "1" and becomes "0" when a carry occurs, and this signal is input to the D terminal of flip-flop F40 synchronized with the clock pulse CP. Therefore, when the subtraction count by the down counter 642 is completed, a signal synchronized with the clock pulse CP is output from the Q terminal of the flip-flop F40 to the signal line 25 to indicate this fact.

On the other hand, this down counter 642 has a NAND gate NAND31 connected to its clock terminal CLK.
The FP signal is input through NAND29 at the CC5 signal time, and the NAND gate NAND31,
The D0 terminal output of the frequency dividing circuit 620, that is, the signal input of the signal line 30 is received through the NAND 30 at the time CC6.

The FP signal indicates a pulse signal from a pulse plate that outputs a pulse signal when the plate moves a predetermined amount as a function of displacement from the initial position in conjunction with an aperture control mechanism (not shown), and the number of FP signals is This represents the restriction position of the aperture.

The operation of this down counter 642 will be explained.

This down counter 642 takes in and stores the output data of the narrowing down stage number control register 628 from the J0 to J7 terminals through the data selector 632 during the time of the CC3 signal. When transitioning from this state to the CC5 signal time, the NAND gate NAND3
0, FP signal is input through NAND31,
The aperture stage number control data AV stored at the time of the CC3 signal is counted down according to the FP signal, and as a result, when the subtraction count is completed, CO2
The terminal output signal transitions from "1" to "0". At this point, the diaphragm regulating member has moved from the initial position to a position where the diaphragm amount corresponding to the diaphragm stage number control data AVs is preset. At this time, the fact that the CO2 terminal output signal has become "0" is detected by the flip-flop F40, and the aperture regulating member connects the aperture stage number control data AVs from the Q output terminal to the signal line 25.
A signal is output in synchronization with the clock pulse CP to indicate that it has moved to the position corresponding to CP.

This down counter 642 also controls the shutter second control register 626 at the time of the CC4 signal.
The Q5 to Q7 terminal output data, that is, the data below the decimal point of the shutter time control data TV is fetched from the J0 to J3 terminals through the data selector 632 and stored. Next, when moving to the CC6 signal time,
The D0 terminal output of the frequency divider circuit 620 is input to the clock terminal CLK from the signal line 30 through the NAND gates NAND30 and NAND31.
This signal line 30 is connected to the CC6 time as described above.
16KHz pulse signal as shutter time control data
It is a pulse with a pulse period that is divided based on the integer stage information of the TV. Therefore, the digital value according to the TV's decimal stage information stored at the time of the CC4 signal is converted into a pulse with a frequency according to the integer stage. Follow the signal
It counts down, and as a result, when the subtraction count ends, the CO2 terminal output signal changes from "1" to 0.

In this way, by counting down the value of the decimal stage of the shutter seconds until it reaches zero using a pulse with a frequency corresponding to the value of the integer stage, the shutter seconds can be set.
The TV is expanded to real time and the shutter seconds are timed. At this time, the fact that the CO2 terminal output signal becomes "0" is detected by the flip-flop F40, and from the Q output terminal to the signal line 25,
A signal is output in synchronization with the clock pulse CP to indicate that the real time corresponding to the shutter time control data TVs has elapsed since entering the state of the CC6 signal.

FIG. 5 is a circuit diagram showing a part of the circuit section constituting the control circuit along with FIGS. 2 and 4, which constitutes a logic circuit for obtaining the control signals CC0 to CC7 mentioned above. .

Reference numeral 990 in the figure is a decoder, which includes flip-flops F32, F33, F34.
The Q outputs FC1, FC2, and FC3 are decoded and output as signals CC0 to CC7. These flip-flops F32,F
33 and F34 are both synchronized with the clock pulse CP.

Now, set the flip-flop F32 set condition to SFC1, reset condition to RFC1, flip-flop F33 set condition to SFC2, reset condition to RFC2, flip-flop F34.
Set conditions to SFC3, reset conditions to RFC3,
All the flip-flops F32, F33, F
34 direct reset condition is set as FDR.

The fact that the above FDR condition holds means that flip-flops F32, F33, and F34 are reset regardless of the clock pulse CP, and therefore,
The decoder 990 outputs "1" as the CC0 signal. That is, the system will be placed or returned to the state of the CC0 signal.

This FDR condition is established when the power is turned on.
The power up clear signal PUC is input, the state of the CC2 signal, that is, the EDSP signal input when a malfunction is detected during self-timer operation becomes "1", or the film winding is completed. The winding completion detection signal WNUP signal from the switch, which detects the film winding operation and reverses the switching state when winding is completed, does not indicate "1" but is "0", and the CC7 signal does not indicate "1" but "0". This is true when the winding is completed in the CC7 signal state, the WNUP signal is "1", and the time corresponding to 2 Hz has elapsed.

By the way, FDR is established when the CC7 signal is "1," the WNUP signal is "1," and the 2Hz signal is "1." This means that the film winding is completed while the shutter release button 18 is kept pressed. The purpose is to enter the next control state after a period of time for the next calculation result to be loaded into the display register. This is an important condition when performing continuous shooting while keeping 18 pressed.

Note that the AND gates AND85, AND86, and
AND87, or gate OR47, OR48,
OR49 and inverter INV42.

The fact that the condition of the CC2 signal is satisfied means that the flip-flop F33 is placed in the set state,
This means that flip-flops F32 and F34 are placed in the reset state, and for that purpose SFC2
It is necessary that the following conditions are satisfied.

That is, in order to create the CC2 signal state, the EDSP signal must be “0” in the CC0 signal state, and the FDR
When the following conditions are not met, the signal from the signal line 17 is "1", that is, the calculation has been completed, and the signal from the signal line 23 is "1", that is, data transfer is not performed. The condition of SFC2 is satisfied when the shutter release button 18 is pressed when the shutter release button 18 is not in use, the switch linked to the release button is turned on, and the SR signal as the on signal of the rear switch becomes "1". It is necessary for the following to hold true.

At this time, the lever 22 is moved to the self-position 28.
If the SELF signal, which is the on signal of the switch that is turned on by adjusting the lever 22 to the self position 28, is “0”, the condition of SFC1 is also satisfied, so the system teeth
The state of the CC0 signal changes to the state of the CC3 signal without passing through the state of the CC2 signal.

If the SELF signal becomes "0" and the SR signal becomes "0" while in the state of the CC2 signal, it is assumed that the self-timer shooting has been canceled, and the conditions of RFC2 are met, and the system will return to the CC0 state.

On the other hand, when the CC2 signal is in the state, the signal on the signal line 30 becomes “1”, that is, the frequency divider circuit 620
When "1" is output from the D0 terminal and the signal on the signal line 23 is "1", the SFC1 condition is satisfied and the system shifts to the CC3 signal state.

The state of the CC3 signal changes to the state of the CC1 signal when the signal on the signal line 30 becomes "1", that is, when 2 msec has elapsed and the conditions of RFC2 are satisfied. It is.

The transition from the CC1 signal state to the CC5 signal state occurs when the signal on the signal line 30 becomes "1", that is, when 2 msec has elapsed.
This is when the condition of SFC3 is satisfied.

Transitioning from the state of the CC5 signal to the state of the CC4 signal means that the MDSP signal, which normally indicates "0", changes to "0".
Then, when the signal on the signal line 25 becomes "1", that is, when the aperture regulating member moves by an amount corresponding to the aperture stage number control data AVs, or when the signal on the signal line 3
When the 0 signal becomes "1", that is, when 30 msec has elapsed, the condition of RFC1 is satisfied.

The transition from the CC4 signal state to the CC6 signal state occurs when the front shutter curtain starts running, the switch that detects shutter running is reversed, and the CTST signal as an inverted signal becomes "1", and the SFC2 signal changes to "1". This is when the conditions are met.

The state of the CC6 signal shifts to the CC7 signal state when the BDSP signal indicating the valve mode is "0", that is, it is not the valve mode, and the output of the signal line 25 becomes "1", that is, when the shutter second When the real time measurement corresponding to the control data TVs ends,
This is when the condition of SFC1 is satisfied.

In addition, in the state of the CC6 signal, if the BDSP signal is "1" and the SR signal is "0", the RFC
Conditions 2 and RFC4 are satisfied, and the system returns to the CC0 signal state.

Furthermore, when the SR signal becomes "0" in the state of the CC7 signal, the conditions of RFC1, RFC2, and RFC4 are satisfied, and the system returns to the state of the CC0 signal.

In addition, the gates involved in SFC1 are AND gates AND79, AND80, AND87, NAND gates NAND5, NSND6, NAND7,
NAND16, NAND23, inverter INV3
6, INV37, INV38, INV39, and flip-flop F35.

Also, those involved in RFC1 are and
Gate AND81, AND90, NAND gate
NAND8, NAND9, NAND10, NAND1
1, NAND19, inverter INV44, flip-flop F31, OR gate OR50,
This is a logical configuration based on OR51 and OR52.

Also involved in SFC2 are NAND gates NAND17, NAND18, NAND24,
Flip flop F30, F31, inverter
This is a logical configuration based on INV48.

Also involved in RFC2 is Nando
Gate NAND12, NAND14, NAND20,
NAND8, NAND9, flip-flop F3
6, AND gate AND81, AND88, OR gate OR50, inverter INV37, INV
This is the logical configuration based on 38 and INV44.

Also involved in the SFC3 are a NAND gate NAND13, an AND gate AND89, an OR gate OR51, an inverter INV43, and a flip-flop F37.

Also involved in RFC3 is Nando
Gate NAND9, NAND14, NAND21,
This is a logic circuit based on inverter INV37.

A direct reset signal to the direct reset terminal R of the frequency dividing circuit 620 is applied through the signal line 29.

The conditions for outputting “1” to this signal line 29 are: when the SR signal becomes “0” in the state of the CC7 signal, the conditions of SFC1, the conditions of SFC2, the conditions of RFC
The contents of the frequency divider circuit 620 are all cleared by this direct reset signal during one bit of the first clock pulse CP after the conditions 2 and 3 are satisfied. It is something that will be done.

Note that the NAND gates NAND9, NAND9, are involved in outputting “1” to this signal line 29.
NAND22, NAND25, NAND26,
NAND27, NAND28, inverter INV3
7. It has a logic configuration consisting of INV40 and an OR gate OR50.

Further, 396 is a shutter release means, 398
Reference numeral 400 indicates an aperture control means, and 400 a shutter speed control means, each of which is supplied with an energizing signal.
An energization signal is given to the aperture control means 398 at the time of the CC1 signal, an energization signal is given to the aperture control means 398 at the time of the CC3, CC1, and CC5 signals, and a energization signal is given to the shutter speed control means 400 at the time of the CC5, CC4, and CC6 signals. An energizing signal is given at the time.

In order to realize this operation, the CC1 signal is directly applied to the shutter/release means 396, and the AND signal is applied to the aperture control means 398.
The FC1 signal and the inverted signal of the CC7 signal by the inverter INV41 are applied to the shutter speed control means 400 through the gate AND82.
The FC3 signal and the output signal of the inverter INV41 are applied through the AND gate 82.

FIG. 6 shows a blinking control circuit for the LED 32 as the self-timer operation display device.

In Fig. 6, 800 is a 15-stage frequency divider circuit that receives a 64KHz clock pulse CP.
A 2Hz on/off signal is generated by dividing the frequency by 15 steps. This 2Hz signal is an AND gate AND100
is given to.

Reference numeral 808 is a battery check circuit which is configured to output a "1" signal when the remaining battery level is sufficient during battery check.

The output of the battery check circuit 808 is
It is applied together with the CC2 signal to the AND gate AND100 via the OR gate OR100, and the output signal of this AND gate AND100 is applied to the LED drive circuit 404.

In this configuration, when the CC2 signal is "1" while the self-timer is operating, or when the battery check shows that the remaining battery capacity is sufficient, the LED drive circuit 404 is turned on at 2 Hz.・
An off signal is given, and therefore the LED display 32 flashes.

Next, the operation of the present invention having the above configuration will be explained using the flow shown in FIG.

When the power is on, the flip-flops F32 to F34 are reset by the PUC signal, so that they are in the CC0 signal state. In this state, photometry
Operations before normal photographing, such as calculation and display, are repeatedly executed.

It is assumed that the release button 18 is pressed from this state. Assuming that the select lever 22 is now set at the 28th position, that is, the selection setting position, when the release button is pressed, the SR signal becomes "1" and the SELF signal also becomes "1". As a result, "1" is output from the AND 79 shown in FIG.
At this time, if the signal EDSP indicating malfunction is "0" and the arithmetic operation at CC0 has been completed, then
Since 1 is input from 17, AND80 outputs "1".

“1” from this AND80 is input to NAND17. On the other hand, CC0 is "1", and approximately at the same time as the above calculation is completed, the calculated value is transferred to the display and control register, and "1" is input indicating that the transfer has been completed, so NAND17 becomes “0”, flip-flop F33 is set via NAND24, and decoder 990 outputs CC2.
Output a signal.

Furthermore, when the SELF signal is “0”, NAND5,
Since flip-flop F32 is also set via NAND15, NAND16, and NAND23, decoder 990 outputs the CC3 signal. That is, the lever 22 is set to self-time mode.
When the release button is pressed only when the CC0 signal is set, the CC0 signal changes to the CC2 signal state.
Also, since a pulse is output from 29 at this time, the frequency divider circuit 620 in FIG. 2 is reset. When the state shifts to the CC2 signal state as described above, a pulse with a period of 16 seconds is output from the output D0 of the frequency divider circuit as described above, and at the rising edge of this pulse, that is, 8 seconds after the shift to CC2, becomes “1”. As a result, AND87 becomes "1", NAND6 becomes "0", and NAND15 becomes "1". or,
In the CC2 signal state, the above-mentioned photometry and calculation operations are repeated, and "1" is repeatedly output from 23, so NAND16 is "0" and NAND
23 becomes "1" and sets flip-flop F32. With this, Flip Flop F3
2, F33 transitions to the set state, so the decoder 990 outputs the CC3 signal. In this CC2 signal state, the LED 32 blinks as described above to indicate that the self-timer is in operation.

Also, the lever 22 can be moved to the self position 28 during the CC2 signal.
When removed from the SELF signal, the SELF signal becomes "0". At this time, NAND8 becomes “0” and NAND20 becomes “1”
becomes. Flip-flop F33 is thus reset and returns to the CC0 signal state.

Therefore, by removing the lever 22 from the self-time position during the self-time operation, the self-mode can be reset during the self-time operation.

After transitioning to the CC3 signal state as described above, the transition to the CC1 signal state occurs after a certain period of time has elapsed.

When the state changes to CC3 signal, the aperture control means 39
8 is energized, and the aperture regulating member is clamped.
The mechanism is biased toward the clamp release side, and the regulating member becomes movable.

When the state shifts to CC3, the frequency divider circuit 620 outputs a pulse with a 4mssc period from the output D0 as described above, and CC3
When 2 msec has passed after the transition, the rising edge signal of the above pulse is output from 30.

As a result, AND88 outputs "1", setting flip-flop F36, causing NAND12 to output "0" and NAND20 to output "1", resetting flip-flop F33, and transitioning to the CC1 signal state. In the CC3 signal state, the aperture value information AUS in the register 628 in FIG. 4 is taken into the down counter 642.

In the state of the CC1 signal, the shutter release means 396 is energized to operate the trigger mechanism for starting the mechanical sequence. The state of this CC1 signal is also held for a predetermined period of time in the same way as CC3, and is then transferred to the state of the next CC5 signal (), but depending on the operation of the trigger mechanism, the mechanical sequence of the camera device starts running.

The state of the CC5 signal is an aperture control cycle, and operations such as raising the mirror and moving the aperture regulating member are performed depending on the mechanical sequence. In the state of this CC5 signal, the pulse signal FP is output according to the amount of movement of the aperture regulating member.
is input to the counter 642 in FIG.
If it matches AVs, CC4 will change from the state of this CC5 signal.
A transition to the signal state () is performed, but at this time, the energization to the aperture control means 398 is stopped, and the aperture regulating member is clamped to restrict its movement.

In addition, when the transition from CC5 to CC4 is completed, the above-mentioned aperture information down-count is completed and "0" is output from terminal CO2, and "1" is output from Q of F40, and AND81 in FIG. 5 becomes "1". output and NAND
10 outputs "0", NAND19 outputs "1", flip-flop 32 is reset, and only flip-flop F34 is set to the CC4 signal state. do.

When the state of the CC5 signal is entered, the shutter speed control means 400 is energized to restrict the movement of the shutter rear curtain, and the shutter rear curtain is prohibited from running after CC5.

In addition, in the state of this CC5 signal, the aperture narrowing operation to the position regulated by the aperture regulating member is performed in parallel, and the aperture control is completed.

Next, when the CC5 signal changes to the CC4 signal state, the front shutter curtain starts running as a mechanical sequence progresses. Exposure of the film surface does not start immediately when the leading shutter curtain starts running, but there is a mechanical delay time, so the state of the CC4 signal is changed to compensate for this time. It has been set.

When the leading shutter curtain starts running as described above, the CTST signal is sent to the flip-flop F3 in Fig. 5.
0 is input, F30 is set, “1” is output from F31, and NAND18 becomes “0”.
NAND24 outputs "1".

As a result, flip-flop F33 is set, F34 and F33 are set to the set state, and the state shifts to the CC6 signal state.

The state of the CC6 signal is a shutter speed control cycle, and after entering the state of the CC6 signal, real time is measured based on the shutter speed control data TV, and the time corresponding to the shutter speed control data TV is measured. After this time, the state of the CC6 signal shifts to the state of the CC7 signal ().In other words, in the CC6 signal state, the frequency dividing circuit 62 in
A pulse with a frequency corresponding to the integer stage information of shutter seconds is output from the output DO of 0, and
In the down counter 642 in the figure, the decimal point information of the TV information from the register 626 is input in the CC4 signal state, and in the CC6 signal state, this decimal point information is used as a pulse with a frequency corresponding to the integer stage information of the shutter seconds. The time until the contents of the counter 642 become zero during the down count is the time corresponding to the shutter seconds.

After this time has elapsed, Q of flip-flop F40 in FIG. 4 outputs "1", which in turn
Input to NAND7, NAND7 outputs “0”,
As a result, NAND23 outputs "1". As a result, flip-flop F32 is set and the output of decoder 990 is transferred to CC7.

In the state of the CC7 signal, the shutter speed control means 400, which was previously energized, is de-energized, the shutter trailing curtain starts, and the exposure of the film surface is stopped. Note that after the shutter trailing curtain has finished running, the mechanical sequence includes a quick return of the mirror and aperture drive lever.

By the way, the BDSP signal is "1" in valve mode.
In this state, as long as the signal SR from the switch SW2 linked to the shutter release button 18 is "1", the state of the CC6 signal is maintained.
When the SR signal becomes "0", the state of the CC6 signal returns to the state of the CC0 signal (XII). This function is based on the fact that the release button 18 is used to directly manually control the shutter speed in the bulb photography mode.

Furthermore, the state of the CC7 signal is a so-called post-display state in which the data that forms the basis of the exposure control that has been performed can already be checked in the viewfinder even after shooting is completed. Note that the state of this CC7 signal is determined when the signal SR is "1" at the time of transition from the CC6 signal state to the CC7 signal state, that is, if the shutter release button 18 is not continuously pressed. When the signal SR becomes "0" in the intervening state, the state immediately returns to the state of the CC0 signal (XI).

Furthermore, if the signal SR is already "0" at the time of transition from the CC6 signal state to the CC7 signal state, that is, if the shutter release button 18 has already been released, the system will
After transitioning to the CC7 signal state, it immediately returns to the CC0 state.

Furthermore, even if the shutter release button 18 is kept pressed down while the CC7 signal is on, if the film is wound manually or by a motor drive, the system CC7 signal will change to the CC0 signal. The situation will be restored. this is,
When continuous photographing is performed using a motor drive device, holding the shutter release button 18 in a depressed state is an important function.

As described above, the present invention allows the user to deselect the self-timer mode using the operating member when resetting the self-timer mode during self-timer timing after setting the self-timer mode using the self-timer setting operating member. For example, since the self-timer mode during timekeeping can be reset, it is possible to provide a self-timer device with extremely good operability.

[Brief explanation of the drawing]

FIG. 1 is a six-sided view showing an example of the external appearance of a camera having a self-timer device according to the present invention, and FIG.
FIG. 3 is a circuit diagram showing a part of the control circuit of the camera shown in FIG. 1, FIG. 3 is a circuit diagram showing the circuit configuration of the frequency dividing circuit 620 shown in FIG. 2, and FIGS. 6 is a circuit diagram showing a drive circuit of the self-timer operation display device of the camera shown in FIG. 1, and FIG. 7 is a circuit diagram showing the operation of the camera according to the present invention. It is an explanatory diagram for explanation. 22... Selector lever, 620... Frequency dividing circuit, 618A to 618D... Select gate,
642...Counter, F32-F34...Flip/Flop.

Claims (1)

[Scope of Claims] 1. A self-timer mode selection means is provided, and the shutter release operation is performed after the self-timer time has elapsed by putting the release operating member into an operating state with the self-timer mode set by the selection means. In a camera having a self-timer device, a self-mode signal is formed when the self-timer mode is selected by the selection means, and a non-self-mode signal is formed when the self-timer mode is not selected by the selection means. A mode signal forming means for forming a signal, a release operation signal forming means for detecting the operation of the release operation member and forming a release operation signal, and a plurality of different set states, and the self mode signal and the non-self mode signal. , a sequence circuit that moves from the current set state to the next set state in response to a release operation signal, and causes the camera to perform a predetermined operation in each set state, when the circuit is in the first set state. , transitioning the set state to a second set state upon detection of the non-self mode signal and the release operation signal;
Further, when in the first set state, the set state is shifted to the third set state upon detection of the self-mode signal and the release operation signal, and the set state is shifted to the third set state in response to the self-timer end signal. a sequence set state determination circuit that moves from the first set state to the second set state and further moves to the first set state upon detection of the non-self mode signal in the third set state; magnet means for performing a release operation upon transition to the third set state, and self-timer timing means for measuring a self-timer time upon transition to the third set state and outputting the self-timer end signal after the self-timer time has elapsed. , operating the release operating member and determining the selection state of the self-timer mode in the first set state;
A release operation is performed in the second set state, a self-timer operation is performed in the third set state,
A camera characterized in that the self-timer operation is canceled when the selection of the self-timer mode by the selection means is canceled during the self-timer operation.