JPS6358491B2 - - Google Patents
Info
- Publication number
- JPS6358491B2 JPS6358491B2 JP56127587A JP12758781A JPS6358491B2 JP S6358491 B2 JPS6358491 B2 JP S6358491B2 JP 56127587 A JP56127587 A JP 56127587A JP 12758781 A JP12758781 A JP 12758781A JP S6358491 B2 JPS6358491 B2 JP S6358491B2
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- switch element
- capacitor
- switch
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000004965 Hartree-Fock calculation Methods 0.000 description 13
- 101710083129 50S ribosomal protein L10, chloroplastic Proteins 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
- H03H19/004—Switched capacitor networks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Filters That Use Time-Delay Elements (AREA)
Description
【発明の詳細な説明】
本発明は、MOS構造の集積回路（以下、ICと
略記する。）で形成されているスイツチトキヤパ
シタフイルタ（以下、SCFと略記する。）の低消
費電力化に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to reducing the power consumption of a switch capacitor filter (hereinafter abbreviated as SCF) formed of an integrated circuit (hereinafter abbreviated as IC) with a MOS structure.
従来、モノリシツクSCFにおいては、その構成
要素である演算増幅器は、常に１個当り100〜
1000μAの電流が流れるように構成されていた。
このため、SCFを用いたアナログデイジタル混載
集積回路においては、デイジタル部分が著しく低
電力化されている一方でSCFは低電力下を妨げる
要因を成していた。本発明はかかる欠点を除去し
たものであり、アナログデイジタル混載集積回路
におけるSCFの大幅な低電力化を達成するもので
ある。 Conventionally, in a monolithic SCF, each operational amplifier, which is a component, always has a
It was configured to carry a current of 1000 μA.
For this reason, in analog-digital hybrid integrated circuits using SCFs, while the digital portion has been significantly reduced in power consumption, the SCFs have been a factor that hinders lower power consumption. The present invention eliminates these drawbacks and achieves a significant reduction in the power consumption of the SCF in an analog-digital hybrid integrated circuit.
以下、LC梯子形ローパスフイルタをシミユレ
ートしたSCFを例にとり、図面を用いて本発明を
詳細に説明する。第１図にLC梯子形ローパスフ
イルタの回路図の一部を示す。同図で１０１及び
１０３はインダクタを、１００及び１０２はキヤ
パシタをそれぞれ示し、１０４，１０５，１０
６，１０７はいずれも節点を示す。１０１，１０
２の素子値をそれぞれＬ(H)、Ｃ（Ｆ）とし、節点
１０４からみた節点１０５の電位をV1（Ｖ）、イ
ンダクタ１０１を通つて節点１０５から節点１０
６へ流れる電流をI2(A)、節点１０４からみた節点
１０６の電位をV3（Ｖ）、インダクタ１０３を通
つて節点１０６から節点１０７へ流れる電流をI4
(A)とすると、インダクタ１０１、キヤパシタ１０
２において次式が成り立つ。 Hereinafter, the present invention will be explained in detail with reference to the drawings, taking as an example an SCF that simulates an LC ladder-type low-pass filter. Figure 1 shows part of the circuit diagram of the LC ladder type low-pass filter. In the figure, 101 and 103 indicate inductors, 100 and 102 indicate capacitors, and 104, 105, 10
6 and 107 both indicate nodes. 101,10
2 element values are respectively L(H) and C(F), the potential of node 105 seen from node 104 is V 1 (V), and the potential of node 105 from node 105 through inductor 101 is
6 is I 2 (A), the potential of node 106 seen from node 104 is V 3 (V), and the current flowing from node 106 to node 107 through inductor 103 is I 4
(A), inductor 101, capacitor 10
2, the following formula holds true.
I2＝V1−V3／sL ……(1)
V3＝I2−I4／sC ……(2)
ただし、Ｓ＝j2πf（ｊ＝√−１、ｆは信号周波
数）とする。式(1)、(2)を従来の方法によつてSCF
に置き換えると第２図ａに示すようになる。第２
図ａにおいて、２０１，２０２はMOS演算増幅
器であり、正電源２０３，２０５と負電源２０
４，２０６の間に接続されている。この他２０
７，２０８は接地（グランド）、２０９，２１０，
２１１，２１２はキヤパシタ、２１３，２１４，
２１５，２１６，２１７，２１８，２１９，２２
０はアナログスイツチ（トランスフアーゲート又
はトランスミツシヨンゲート）を各々示してい
る。 I2 = V1 - V3 /sL...(1) V3 = I2 - I4 /sC...(2) However, S=j2πf (j=√-1, f is the signal frequency). Expressions (1) and (2) are converted to SCF using the conventional method.
When replaced with , it becomes as shown in FIG. 2a. Second
In figure a, 201, 202 are MOS operational amplifiers, positive power supplies 203, 205 and negative power supplies 20
4,206. 20 others
7,208 is ground, 209,210,
211, 212 are capacitors, 213, 214,
215, 216, 217, 218, 219, 22
0 indicates an analog switch (transfer gate or transmission gate).
第２図ａにおいて、アナログスイツチ２１３，
２１４，２１９，２２０は第２図ｂに示すクロツ
ク信号CL１でスイツチングされ、アナログスイ
ツチ２１５，２１６，２１７，２１８はクロツク
信号CL２でスイツチングされている。（ただしア
ナログスイツチ２１３〜２２０はクロツク信号が
ハイでオン、ローでオフするものとする。）端子
２２１にはV1（Ｖ）に相当する信号が、また端子
２２３にはI4(A)に相当する信号が入力されてい
る。この結果、節点２２２にはI2(A)に相当する信
号が、また、節点２２４にはV3（Ｖ）に相当する
信号が得られる。ところで、第２図ｂにおいて
CL１がハイの期間をＰ１、CL２がハイの期間を
Ｐ２とすると、演算増幅器２０１を用いて電荷の
転送が行われるのはＰ２の期間のみであり、演算
増幅器２０２を用いて電荷の転送が行われるのは
Ｐ１の期間のみである。電荷転送が行われていな
い期間においてはキヤパシタ２１０，２１２に蓄
えられた電荷の保持が行われているだけである。
従つて電荷転送が行われていない期間中は演算増
幅器をオフ状態即ち電流が全く流れない状態にし
ておいてもフイルタの伝送特性に影響はない。こ
の点に鑑みて、本発明では第１図に示すLC梯形
フイルタを第３図ａのごとく実現する。第３図ａ
において、記号２０１〜２２４は第２図ａの同一
記号のものと同じものを表わす。３０１，３０
２，３０３，３０４，３０５，３０６はいずれも
アナログスイツチ（トランスフアーゲート又はト
ランスミツシヨンゲート）を表わす。第３図ａに
おいてアナログスイツチ３０１，３０２，３０５
はCL２に同期したクロツク信号CL２０によつて
スイツチングされ、アナログスイツチ３０３，３
０４，３０６はCL１に同期したクロツク信号CL
１０によつてスイツチングされる。CL１０とし
てCL１を、CL２０としてCL２を用いてもよい。
また、クロツク信号の伝ぱん遅延、電源投入直後
の演算増幅器の不安定性等を考慮してCL１０と
して第３図ｂに示すCL３、CL２０として第３図
ｂに示すCL４のごとく余裕をもたせた信号を用
いてもよい。（ここで、アナログスイツチ３０１，
３０２，３０５はCL２０がハイのときオン、ロ
ーのときオフとなり、アナログスイツチ３０３，
３０４，３０６はCL１０がハイのときオン、ロ
ーのときオフとなるものとする。）SCFを第３図
ａのごとく構成することにより、SCFを構成する
演算増幅器で消費される電力は第２図ａのような
従来の構成に比べて1/2以下に低減される。本発
明の構成はLC梯形フイルタをシミユレートした
リープフロツグ形のSCFすべてに適用できる。第
４図に本発明に用いるアナログスイツチを付加し
た演算増幅器の一構成例を示す。同図において、
４２１は反転入力端子、４２２は非反転入力端
子、４２３は出力端子、４２４は正電源、４２５
は負電源である。ＰチヤネルMOSFET４０１及
びＮチヤネルMOSFET４０２はバイアス回路を
形成し節点４２０には定電位が得られる。Ｐチヤ
ネルMOSFET４０３，４０４及びＮチヤネル
MOSFET４０５，４０６，４０７は差動増幅段
を、ＰチヤネルMOSFET４０８及びＮチヤンネ
ルMOSFET４０９はレベルシフト段を形成す
る。Ｐチヤネルアナログスイツチ４１０及びＮチ
ヤネルアナログスイツチ４１１は他のMOSFET
４０１〜４０９に比べチヤネル幅／チヤネル長を
十分大きくとりコンダクタンス係数を十分に大き
くする必要がある。端子４２６には、演算増幅器
のオン、オフを制御するクロツク信号CL１０ま
たはCL２０が入力される。尚、アナログスイツ
チは第４図のごとく正負両電源に付加される必要
はなく、正又は負のいずれか一方の電源に付加さ
れていれば十分である。 In FIG. 2a, analog switch 213,
The analog switches 214, 219, and 220 are switched by the clock signal CL1 shown in FIG. 2b, and the analog switches 215, 216, 217, and 218 are switched by the clock signal CL2. (However, the analog switches 213 to 220 are assumed to be turned on when the clock signal is high and turned off when the clock signal is low.) A signal corresponding to V 1 (V) is supplied to the terminal 221, and a signal corresponding to I 4 (A) is supplied to the terminal 223. A corresponding signal is being input. As a result, a signal corresponding to I 2 (A) is obtained at node 222, and a signal corresponding to V 3 (V) is obtained at node 224. By the way, in Figure 2b
Assuming that the period when CL1 is high is P1 and the period when CL2 is high is P2, charge transfer is performed using the operational amplifier 201 only during the period P2, and charge transfer is performed using the operational amplifier 202. This occurs only during the P1 period. During the period when charge transfer is not performed, the charges stored in the capacitors 210 and 212 are simply held.
Therefore, even if the operational amplifier is kept in an off state, that is, in a state in which no current flows during a period when charge transfer is not performed, the transmission characteristics of the filter are not affected. In view of this point, in the present invention, the LC trapezoidal filter shown in FIG. 1 is realized as shown in FIG. 3a. Figure 3a
2, symbols 201 to 224 represent the same symbols as those in FIG. 2a. 301,30
2, 303, 304, 305, and 306 all represent analog switches (transfer gates or transmission gates). In FIG. 3a, analog switches 301, 302, 305
is switched by the clock signal CL20 synchronized with CL2, and the analog switches 303, 3
04,306 is the clock signal CL synchronized with CL1
10. CL1 may be used as CL10, and CL2 may be used as CL20.
In addition, in consideration of the propagation delay of the clock signal, the instability of the operational amplifier immediately after the power is turned on, etc., we set a signal with a margin such as CL3 shown in Figure 3b as CL10 and CL4 shown in Figure 3b as CL20. May be used. (Here, the analog switch 301,
302, 305 are on when CL20 is high and off when CL20 is low, and analog switches 303,
304 and 306 are assumed to be on when CL10 is high and off when CL10 is low. ) By configuring the SCF as shown in FIG. 3a, the power consumed by the operational amplifiers constituting the SCF can be reduced to less than 1/2 compared to the conventional configuration as shown in FIG. 2a. The configuration of the present invention can be applied to all leapfrog SCFs that simulate LC ladder filters. FIG. 4 shows an example of the configuration of an operational amplifier to which an analog switch is added for use in the present invention. In the same figure,
421 is an inverting input terminal, 422 is a non-inverting input terminal, 423 is an output terminal, 424 is a positive power supply, 425
is a negative power supply. P-channel MOSFET 401 and N-channel MOSFET 402 form a bias circuit, and a constant potential is obtained at node 420. P-channel MOSFET403, 404 and N-channel
MOSFETs 405, 406, and 407 form a differential amplification stage, and P-channel MOSFET 408 and N-channel MOSFET 409 form a level shift stage. P channel analog switch 410 and N channel analog switch 411 are other MOSFETs.
Compared to 401 to 409, it is necessary to make the channel width/channel length sufficiently large and the conductance coefficient sufficiently large. A clock signal CL10 or CL20 for controlling on/off of the operational amplifier is input to the terminal 426. Note that the analog switch does not need to be attached to both the positive and negative power supplies as shown in FIG. 4, and it is sufficient if it is attached to either the positive or negative power supply.
以上述べたごとく、本発明は、演算増幅器の電
源端子及び電荷の保持を行なつているキヤパシタ
にサンプリングのクロツク信号に同期したクロツ
ク信号でスイツチングされるアナログスイツチを
接続することによりSCF消費電力を大幅に低減す
るものである。 As described above, the present invention significantly reduces SCF power consumption by connecting an analog switch that is switched by a clock signal synchronized with a sampling clock signal to the power supply terminal of the operational amplifier and the capacitor that holds charge. This will reduce the
第１図はシミユレートされるLC梯形フイルタ
の一例。第２図ａは従来構成によるSCFの一例。
第２図ｂは第２図ａのアナログスイツチに印加さ
れるクロツク信号の一例。第３図ａは本発明によ
るSCFの一構成例。第３図ｂは第３図ａのアナロ
グスイツチに印加されるクロツク信号の一例。第
４図は本発明に用いられる演算増幅器の一構成
例。
Figure 1 shows an example of a simulated LC trapezoidal filter. Figure 2a shows an example of an SCF with a conventional configuration.
FIG. 2b is an example of a clock signal applied to the analog switch of FIG. 2a. FIG. 3a shows an example of the configuration of the SCF according to the present invention. FIG. 3b is an example of a clock signal applied to the analog switch of FIG. 3a. FIG. 4 shows an example of the configuration of an operational amplifier used in the present invention.
Claims (1)
のキヤパシタと前記演算増幅器の入力との間に接
続され周期的にオン・オフする第１のスイツチ素
子と、前記演算増幅器の入出力間に接続される第
２のキヤパシタとを備えるスイツチトキヤパシタ
フイルタに於いて、周期的にオフ状態となつて前
記演算増幅器に電流を流さないようにする第２の
スイツチ素子を具備し、該第２のスイツチ素子
は、前記第１のスイツチ素子がオン状態にある期
間はオン状態になつて前記演算増幅器に電流を流
すように動作することを特徴とするスイツチトキ
ヤパシタフイルタ。 ２ 前記第２のスイツチ素子は前記演算増幅器と
少なくとも一方の電源端子との間に挿入接続さ
れ、前記第１のスイツチ素子のオン状態の期間を
含む期間はオン状態となることを特徴とする特許
請求の範囲第１項記載のスイツチトキヤパシタフ
イルタ。 ３ 前記演算増幅器の入出力間に前記第２のキヤ
パシタと直列な第３のスイツチ素子を挿入接続
し、該第３のスイツチ素子は前記第２のスイツチ
素子と同一のクロツク信号により制御されること
を特徴とする特許請求の範囲第１項記載のスイツ
チトキヤパシタフイルタ。[Claims] 1. An operational amplifier, a first capacitor, and the first
A switch capacitor filter comprising: a first switch element connected between a capacitor and an input of the operational amplifier and turned on and off periodically; and a second capacitor connected between the input and output of the operational amplifier. A second switch element is provided that is periodically turned off to prevent current from flowing through the operational amplifier, and the second switch element is configured to periodically turn off when the first switch element is turned on. A switch capacitor filter, characterized in that it is in an on state for a certain period of time and operates so as to cause current to flow through the operational amplifier. 2. A patent characterized in that the second switch element is inserted and connected between the operational amplifier and at least one power supply terminal, and is in an on state during a period that includes an on state period of the first switch element. A switch capacitor filter according to claim 1. 3. A third switch element in series with the second capacitor is inserted and connected between the input and output of the operational amplifier, and the third switch element is controlled by the same clock signal as the second switch element. A switch capacitor filter according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12758781A JPS5829214A (en) | 1981-08-14 | 1981-08-14 | Switched capacitor filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12758781A JPS5829214A (en) | 1981-08-14 | 1981-08-14 | Switched capacitor filter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5829214A JPS5829214A (en) | 1983-02-21 |
| JPS6358491B2 true JPS6358491B2 (en) | 1988-11-16 |
Family
ID=14963752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12758781A Granted JPS5829214A (en) | 1981-08-14 | 1981-08-14 | Switched capacitor filter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5829214A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6285509A (en) * | 1985-10-11 | 1987-04-20 | Nec Corp | Oscillator |
| US5030083A (en) * | 1989-12-28 | 1991-07-09 | Tigers Polymer Corporation | Apparatus for manufacturing a hollow synthetic resin product |
-
1981
- 1981-08-14 JP JP12758781A patent/JPS5829214A/en active Granted
Non-Patent Citations (2)
| Title |
|---|
| IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE=1977 * |
| IEEE JOURNAL OF SOLID-STATE CIRCUITS=1977 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5829214A (en) | 1983-02-21 |
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