JPS6359610A - Constant voltage circuit - Google Patents

Constant voltage circuit

Info

Publication number
JPS6359610A
JPS6359610A JP20443486A JP20443486A JPS6359610A JP S6359610 A JPS6359610 A JP S6359610A JP 20443486 A JP20443486 A JP 20443486A JP 20443486 A JP20443486 A JP 20443486A JP S6359610 A JPS6359610 A JP S6359610A
Authority
JP
Japan
Prior art keywords
circuit
potential
transistor
turned
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20443486A
Other languages
Japanese (ja)
Inventor
Raisaburo Jitsui
實井 來三郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KOKUSAI SEIGYO KK
Original Assignee
KOKUSAI SEIGYO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KOKUSAI SEIGYO KK filed Critical KOKUSAI SEIGYO KK
Priority to JP20443486A priority Critical patent/JPS6359610A/en
Publication of JPS6359610A publication Critical patent/JPS6359610A/en
Pending legal-status Critical Current

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  • Electronic Switches (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

PURPOSE:To prevent chattering by turning off a voltage switch circuit for overcurrent and causing the output signal for overcurrent to pass a timer circuit and preventing a circuit from being operated with a momentary surge current or the like. CONSTITUTION:When an overcurrent flows to a load, the potential between both ends A and B of a resistance 31 rises, and this potential acts upon the base of a transistor TR 3a as an output signal (a) to turn on the TR 3a, and charging of a capacitor 62 is started through a resistance 61 of the timer circuit. When the rise of the potential continues over a certain time, the potential of the capacitor 62 rises; and when it exceeds a certain value, a TR 7c is turned on, and the potential of an output terminal 70 falls, and an output signal (b) of the output terminal 70 becomes zero. Then, TRs 8a and 8b are turned off, and a TR 2a is turned off also, and the current of the circuit is broken. Consequently, a resistance 11 is prevented from being burnt off.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は定電圧回路、特に回路基板にした定電圧回路に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a constant voltage circuit, and particularly to a constant voltage circuit formed on a circuit board.

〔従来の技術〕[Conventional technology]

従来の定電圧回路は第3図(イ)示のように直流電源回
路1より定電圧電源回路4を介して出力端子5に接続し
ていた。なお第3図(ロ)示のように直流電源回路1と
定電圧電源回路4との間に定電流回路9を挿入すること
もあった。
In the conventional constant voltage circuit, a DC power supply circuit 1 is connected to an output terminal 5 via a constant voltage power supply circuit 4 as shown in FIG. 3(A). Incidentally, as shown in FIG. 3(b), a constant current circuit 9 was sometimes inserted between the DC power supply circuit 1 and the constant voltage power supply circuit 4.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし負荷回路のショート等により過電流が流れると直
流電源回路1の抵抗11(第2図参照)が切れる欠点が
あった。
However, there is a drawback that the resistor 11 (see FIG. 2) of the DC power supply circuit 1 is disconnected when an overcurrent flows due to a short circuit in the load circuit or the like.

本発明はかかる欠点を除去するもので過電流時には回路
を遮断するようにしたものである。
The present invention eliminates this drawback by cutting off the circuit in the event of overcurrent.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は直流電源回路1は電圧スイッチ回路2゜電流検
出回路3及び定電圧電源回路4を介して出力端子5に接
続し、電流検出回路3の過電流の出力信号aはタイマ回
路6を介して保持回路7に入力し、この保持回路7の信
号すは増幅回路8を介して上記電圧スイッチ回路2に入
力し、それをオフに保持することを特徴とす(る定電圧
回路である。
In the present invention, a DC power supply circuit 1 is connected to an output terminal 5 through a voltage switch circuit 2, a current detection circuit 3, and a constant voltage power supply circuit 4, and an overcurrent output signal a of the current detection circuit 3 is connected to an output terminal 5 through a timer circuit 6. A constant voltage circuit is characterized in that the signal from the holding circuit 7 is inputted to the voltage switch circuit 2 via the amplifier circuit 8 and kept turned off.

〔作 用〕[For production]

負荷回路がショートしたときには電流検出回路3より過
電流の出力信号aが発生し、この出力信号aが一定時間
以上持続したときにタイマ回路6を通して保持回路7よ
り信号すが発生し、この信号すは電圧スイッチ回路2を
オフにする。
When the load circuit is short-circuited, an overcurrent output signal a is generated from the current detection circuit 3, and when this output signal a continues for a certain period of time or more, a signal is generated from the holding circuit 7 through the timer circuit 6. turns off the voltage switch circuit 2.

〔実施例〕〔Example〕

第2図は本発明の一実施例の具体的回路を示すもので、
第1図の各部に相当する部分はそのブロックの符号に数
字又はローマ字をつけて示す。
FIG. 2 shows a specific circuit of an embodiment of the present invention.
Parts corresponding to each part in FIG. 1 are indicated by adding numbers or Roman letters to the code of the block.

第2図においてILは直流電源回路1のトランス、LD
はその両波整流ダイオード、11はその出力側に接続し
た抵抗、12はその平滑コンデンサである。
In Fig. 2, IL is the transformer of DC power supply circuit 1, and LD
is its double-wave rectifier diode, 11 is a resistor connected to its output side, and 12 is its smoothing capacitor.

2aは電圧スイッチ回路2のスイッチングトランジスタ
である。
2a is a switching transistor of the voltage switch circuit 2.

31は電流検出回路3の検出用抵抗、3aはその検出用
抵抗31の両端の電圧を検出増幅するトランジスタであ
る。
31 is a detection resistor of the current detection circuit 3, and 3a is a transistor that detects and amplifies the voltage across the detection resistor 31.

41は定電圧電源回路4の定電圧電源ICである。41 is a constant voltage power supply IC of the constant voltage power supply circuit 4.

4a 、 4bはそのI C41の電流増幅用のトラン
ジスタである。
4a and 4b are transistors for current amplification of the IC41.

出力端子5は+12ボルトの出力端子で50はそのアー
ス端子、51は一12ボルトの出力端子でこの一側の出
力端子51には+側と略同じ回路が接続されている。
The output terminal 5 is a +12 volt output terminal, 50 is its ground terminal, 51 is a -12 volt output terminal, and substantially the same circuit as the + side is connected to the output terminal 51 on one side.

上記トランジスタ3aのコレクタはタイマ回路6(7)
IOKオームの抵抗61と1μフアラドのコンデンサ6
2が接続され、その出力端子には2つの10 Kオーム
の放電用抵抗63 、64が接続される。
The collector of the transistor 3a is the timer circuit 6 (7)
IOK ohm resistor 61 and 1μ Farad capacitor 6
2 is connected, and two 10 K ohm discharge resistors 63 and 64 are connected to its output terminal.

フリップフロップよりなる保持回路7は一対の双安定マ
ルチバイブレークを形成するトランジスタ7a 、 7
bとそれに並列接続された駆動用トランジスタ7c 、
 7dとよりなり、駆動用トランジスタ7Cのベースに
は上記抵抗63 、64の間を接続する。トランジスタ
7aの出力端子70は線71を介して増幅回路8のトラ
ンジスタ8a 、 8bに接続する。トランジスタ8b
の出力端子を前記トランジスタ2aのベースに接続する
The holding circuit 7 consisting of a flip-flop includes a pair of transistors 7a and 7 forming a bistable multi-by-break.
b and a driving transistor 7c connected in parallel thereto,
7d, and the resistors 63 and 64 are connected to the base of the driving transistor 7C. The output terminal 70 of the transistor 7a is connected via a line 71 to the transistors 8a, 8b of the amplifier circuit 8. transistor 8b
The output terminal of the transistor 2a is connected to the base of the transistor 2a.

駆動用トランジスタ7dのベースにはリセット回路10
のトランジスタ10aの出力端子を接続する。
A reset circuit 10 is provided at the base of the driving transistor 7d.
The output terminal of the transistor 10a is connected.

101はリセット回路10の100にオームの抵抗、1
02は10μフアラドのコンデンサで、これら抵抗10
1、コンデンサ102で長い時定数のタイマ回路を構成
する。このタイマ回路の出力端子は抵抗106を介して
トランジスタ10aのベースに接続する。なお抵抗10
7は放電用抵抗である。103,104.105は同リ
セット回路10の初期駆動のための直列抵抗で抵抗10
3.104の間はトランジスタ10aのコレクタに、抵
抗104と105の間は駆動用トランジスタ7dのベー
スにそれぞれ接続される。
101 is an ohm resistor at 100 of the reset circuit 10, and 1
02 is a 10μ Farad capacitor, and these resistors 10
1. The capacitor 102 constitutes a timer circuit with a long time constant. The output terminal of this timer circuit is connected via a resistor 106 to the base of transistor 10a. Note that the resistance is 10
7 is a discharge resistor. 103, 104, and 105 are series resistors for the initial drive of the reset circuit 10;
3.104 is connected to the collector of the transistor 10a, and the resistor 104 and 105 is connected to the base of the driving transistor 7d.

次にこの装置の動作を説明する。Next, the operation of this device will be explained.

電源を印加すると、先ずリセット回路10の抵抗1o3
,1o4.105に電流が流れ、駆動用トランジスタ7
dはオンとなりフリップフロップを構成するトランジス
タ7bのコレクタ電位は0でトランジスタ7aのコレク
タ電位が1となる。これによってその出力端子70の出
力信号すは1となり、この1信号すは線71を通してト
ランジスタ8aに送られる。これによってトランジスタ
8a 、 8bがオンとなり、トランジスタ2aがオン
となり、電流電源回路1の抵抗11よりトランジスタ2
a、抵抗31.定電圧電源回路4の電力トランジスタ4
bを通して出力端子5に電流が流れる。この後リセット
回路10の抵抗101.コンデンサ102よりなるタイ
マ回路が働き、そのコンデンサ102が充電されるとト
ランジスタ10aがオンとなってそのコレクタの出力電
圧がOとなり、駆動用トランジスタ7dがオフの状態に
保持される。
When power is applied, first the resistor 1o3 of the reset circuit 10
, 1o4.105, and the driving transistor 7
d is turned on, and the collector potential of the transistor 7b constituting the flip-flop becomes 0 and the collector potential of the transistor 7a becomes 1. As a result, the output signal at the output terminal 70 becomes 1, and this 1 signal is sent to the transistor 8a through the line 71. As a result, transistors 8a and 8b are turned on, transistor 2a is turned on, and transistor 2 is turned on by resistor 11 of current power supply circuit 1.
a, resistance 31. Power transistor 4 of constant voltage power supply circuit 4
A current flows to the output terminal 5 through b. After this, the resistor 101 of the reset circuit 10. A timer circuit consisting of a capacitor 102 operates, and when the capacitor 102 is charged, the transistor 10a is turned on and the output voltage at its collector becomes O, and the driving transistor 7d is kept in an off state.

負荷に過電流が流れると抵抗31の両端A、Bの電位は
上昇し、この電位は出力信号aとしてトランジスタ3a
のベースに作用し、トランジスタ3aはオンとなり、タ
イマ回路6の抵抗61を通してコンデンサ62に充電が
開始されるが、この電位上昇が持続されない限り、抵抗
63 、64による放電速度が充電速度より速くなるの
でトランジスタ7cはオンとはならない。電位上昇が成
る時間以上持続するとコンデンサ62の電位が上昇し、
成る値を越えるとトランジスタ7cはオンとなり出力端
子70の電位は下がり、出力端子70の出力信号すは0
となる。
When an overcurrent flows through the load, the potential at both ends A and B of the resistor 31 increases, and this potential is applied to the transistor 3a as the output signal a.
The transistor 3a is turned on, and charging of the capacitor 62 is started through the resistor 61 of the timer circuit 6. However, unless this potential rise is sustained, the discharging rate due to the resistors 63 and 64 will be faster than the charging rate. Therefore, transistor 7c is not turned on. When the potential rise continues for a period of time or longer, the potential of the capacitor 62 increases,
When the value of
becomes.

これによってトランジスタ8a 、 8bがオフとなり
、トランジスタ2aもオフとなり、回路の電流は切れる
。したがって抵抗11の焼き切れを防止できる。
As a result, transistors 8a and 8b are turned off, transistor 2a is also turned off, and the current in the circuit is cut off. Therefore, burning out of the resistor 11 can be prevented.

この場合でもリセット回路lOのタイマ回路のコンデン
サ102は充電されたままであるので前述のようにトラ
ンジスタ10aはオン、駆動用トランジスタフdはオフ
のままであるから、スイッチングトランジスタ2aのオ
フ状態は持続する。
Even in this case, since the capacitor 102 of the timer circuit of the reset circuit IO remains charged, the transistor 10a remains on as described above, and the driving transistor d remains off, so the off state of the switching transistor 2a continues. .

電源を切って上記タイマ回路のコンデンサ102の放電
後再び電源を印加すると前述のようにリセット回路10
の抵抗103. 10=1,105に電流が流れ、以下
同様にして出力端子5に電流が流れるものである。
When the power is turned off and the power is applied again after the capacitor 102 of the timer circuit is discharged, the reset circuit 10 is activated as described above.
resistance 103. A current flows to 10=1,105, and a current flows to the output terminal 5 in the same manner.

以上のようにして直流電源回路1の破損を防止するもの
である。
As described above, damage to the DC power supply circuit 1 is prevented.

〔発明の効果〕〔Effect of the invention〕

以上のようにして本発明により過電流時には電圧スイッ
チ回路2がオフとなるので直流電源回路1の破損を防止
できるものであるが、上記過電流時の出力信号aはタイ
マ回路6を通しているので瞬間的なサージ電流等では作
動せず、チャタリングを防止しうるちのである。
As described above, according to the present invention, the voltage switch circuit 2 is turned off in the event of overcurrent, thereby preventing damage to the DC power supply circuit 1. However, since the output signal a at the time of overcurrent is passed through the timer circuit 6, It does not operate under normal surge currents and prevents chattering.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の概略を示すブロック図、第2図はその
一実施例の回路図、第3図(イ) (+7)は従来の回
路の2例を示すブロック図である。 ■・・・・・・直流′改・涼回路、2・・・・・・電圧
スイッチ回路、3・・・・・・電流検出回路、4・・・
・・・定電圧電源回路、5・・・・・・出力端子、a・
・・・・・信号、6・・・・・・タイマ回路、7・・・
・・・保持回路、b・・・・・・信号、8・・・・・・
増幅回路。 答1蘭
FIG. 1 is a block diagram showing an outline of the present invention, FIG. 2 is a circuit diagram of one embodiment thereof, and FIG. 3 (A) (+7) is a block diagram showing two examples of conventional circuits. ■・・・DC' modified cooling circuit, 2... Voltage switch circuit, 3... Current detection circuit, 4...
... Constant voltage power supply circuit, 5 ... Output terminal, a.
...Signal, 6...Timer circuit, 7...
...Holding circuit, b...Signal, 8...
Amplification circuit. Answer 1 orchid

Claims (1)

【特許請求の範囲】[Claims] 直流電源回路は電圧スイッチ回路、電流検出回路及び定
電圧電源回路を介して出力端子に接続し、電流検出回路
の過電流の出力信号はタイマ回路を介して保持回路に入
力し、この保持回路の信号は増幅回路を介して上記電圧
スイッチ回路に入力し、それをオフに保持することを特
徴とする定電圧回路。
The DC power supply circuit is connected to the output terminal via a voltage switch circuit, a current detection circuit, and a constant voltage power supply circuit, and the overcurrent output signal of the current detection circuit is input to the holding circuit via the timer circuit. A constant voltage circuit characterized in that a signal is input to the voltage switch circuit through an amplifier circuit and held in the off state.
JP20443486A 1986-08-29 1986-08-29 Constant voltage circuit Pending JPS6359610A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20443486A JPS6359610A (en) 1986-08-29 1986-08-29 Constant voltage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20443486A JPS6359610A (en) 1986-08-29 1986-08-29 Constant voltage circuit

Publications (1)

Publication Number Publication Date
JPS6359610A true JPS6359610A (en) 1988-03-15

Family

ID=16490472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20443486A Pending JPS6359610A (en) 1986-08-29 1986-08-29 Constant voltage circuit

Country Status (1)

Country Link
JP (1) JPS6359610A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04111609A (en) * 1990-08-31 1992-04-13 Mitsubishi Electric Corp Two-input signal changeover circuit
US8496593B2 (en) 2006-05-26 2013-07-30 Robert Park Needle guide
US8852111B2 (en) 2005-09-02 2014-10-07 Ultrasound Ventures, Llc Ultrasound guidance system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432485A (en) * 1977-08-17 1979-03-09 Otsuka Pharmaceut Co Ltd 3,4-dihydrocarbostyril derivatives and their preparation
JPS59218519A (en) * 1983-05-27 1984-12-08 Koito Mfg Co Ltd Power supply circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432485A (en) * 1977-08-17 1979-03-09 Otsuka Pharmaceut Co Ltd 3,4-dihydrocarbostyril derivatives and their preparation
JPS59218519A (en) * 1983-05-27 1984-12-08 Koito Mfg Co Ltd Power supply circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04111609A (en) * 1990-08-31 1992-04-13 Mitsubishi Electric Corp Two-input signal changeover circuit
US8852111B2 (en) 2005-09-02 2014-10-07 Ultrasound Ventures, Llc Ultrasound guidance system
US8496593B2 (en) 2006-05-26 2013-07-30 Robert Park Needle guide

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