JPS6360551B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which a means for forming a bonding layer is improved.

In recent years, in order to achieve higher speed and higher integration of semiconductor devices, oxide film separation technology, shallow junction formation technology,
Various developments have been made in terms of processes such as multilayer wiring technology. In particular, shallow junction formation techniques reduce junction area, junction capacitance, and series resistance;
Device characteristics can be significantly improved. Further, since bond formation by self-alignment eliminates the need for a photolithographic process, high integration can be easily achieved. However, as the depth of the bonding layer becomes shallower, the side diffusion length becomes shorter, so if the diffusion hole used as a contact hole is washed out and enlarged in the process of depositing the electrode material, other diffusion layers will also be separated from the contact hole. For example, in bipolar transistors, there was a problem in that the emitter-base junction was exposed and short-circuited.

For this reason, conventionally, as shown in FIG. 1, diffusion holes 4 are opened in the silicon oxide film 3 on the n-type epitaxial layer 2 in which the p-type base region 1 is formed, and the base region is formed over the entire surface. After depositing a polycrystalline silicon layer 5 doped with a large amount of impurity (for example, arsenic) of a conductivity type opposite to 1, an n ⁺ type emitter region 6 is formed in the base region 1 by thermal diffusion, and a diffusion hole 4 is formed in the base region 1 by thermal diffusion. A method of manufacturing a bipolar transistor is known in which a polycrystalline silicon layer 5 is left in a larger area to prevent the junction from being exposed, and a short circuit between the base region 1 and the emitter region 6 is prevented during the subsequent formation of the emitter lead-out electrode 7. It is being however,
This method requires a photolithography technique that selectively leaves the polycrystalline silicon layer on the diffusion holes, and a heat treatment process in a high-temperature diffusion furnace. - It has the disadvantage that the base joint moves, making it difficult to control the base width.

Alternatively, as shown in FIG. 2, after forming a diffusion hole 4 in a silicon oxide film 3 on an n-type epitaxial layer 2 in which a p-type base region 1 is formed, a diffusion hole 4 containing a large amount of emitter impurities is formed. There is a method in which a single crystal silicon layer is selectively extended over the entire length of the diffusion hole 4 to form an emitter region 6', and subsequently an emitter extraction electrode 7' is formed. According to this method, the emitter-base junction can be formed without photolithography and without contacting the emitter lead-out electrode, but it requires an advanced technique called selective vapor deposition, which increases the number of steps and increases the cost. Not only this, but also because high-temperature heat treatment is applied during vapor phase growth as in the above method, movement of the collector-base junction occurs as shown by the broken line in FIG. 2, making it difficult to control the base width.

In order to overcome this problem, the present inventor has conducted extensive research to overcome the above drawbacks, and as a result, deposited an amorphous semiconductor layer etc. on a single crystal semiconductor substrate provided with an insulating film having partial openings, When this is irradiated with an energy beam, such as a short-pulse laser beam, a liquid phase phenomenon becomes dominant, and the amorphous semiconductor layer in contact with the single-crystal semiconductor substrate becomes a single crystal using the single-crystal semiconductor substrate as a crystal nucleus, and the insulating film It was determined that the upper amorphous semiconductor layer becomes polycrystalline. On the other hand, when irradiated with a laser beam with a long pulse width, the solid phase phenomenon becomes dominant, and its effect spreads deep into the crystal, electrically activating the ion-implanted layer in the single crystal part, forming a junction, and ionizing it. It was found that the impurity distribution immediately after implantation was preserved.

As a result of further studies based on the above findings, the inventors of the present invention introduced an impurity of conductivity type opposite to that of the single crystal semiconductor substrate through the insulating film on the substrate surface, and further, After forming an opening in the area, an amorphous or polycrystalline semiconductor layer is deposited on the entire surface,
By continuing to irradiate short pulses of laser light, an amorphous or polycrystalline semiconductor layer on an insulating film can be polycrystallized without causing movement of the impurity layer of the semiconductor substrate, and the opening of the insulating film can be made polycrystalline. The amorphous semiconductor layer in contact with the single crystal semiconductor layer through the hole can be made into a single crystal, and a large difference in etching rate and oxidation rate can occur between the converted polycrystalline semiconductor layer and the single crystal semiconductor layer. I understood. However,
After irradiation with laser light, the polycrystalline semiconductor layer is selectively removed by wet etching or low-temperature oxidation, or converted into an oxide, and the single-crystalline semiconductor layer becomes separate and independent, and this layer has a conductivity opposite to that of the substrate. After introducing an impurity into the mold and further introducing an impurity of the same conductivity type as the substrate, the impurity is introduced through the insulating film by irradiating laser light with a multi-pulse width.
It has been found that impurities introduced into the surface of a semiconductor substrate through a single crystal semiconductor and impurities introduced into a semiconductor layer are electrically activated, and a junction can be formed in which the impurity distribution immediately after the impurity introduction is preserved. The result is a highly integrated, highly reliable semiconductor that has shallow junctions that are self-aligned with each other by forming each junction without high-temperature treatment, and prevents short circuits between junctions when forming electrodes. We have found a method that allows the device to be manufactured with high yield.

That is, the present invention includes a step of providing an insulating film on a single-crystal semiconductor substrate of one conductivity type, and then introducing an impurity of a conductivity type opposite to that of the substrate into a surface region of the semiconductor substrate through a limited region of the insulating film; A process of selectively opening holes in the insulating film portion adjacent to the introduction region, and after depositing an amorphous or polycrystalline semiconductor layer on the entire surface, irradiating an energy beam with a short pulse width to pass through the openings in the insulating film. A step of monocrystallizing a portion of the amorphous or polycrystalline semiconductor layer in contact with the single-crystal semiconductor substrate, and selectively removing the semiconductor layer that cannot be monocrystalized by performing an etching process, or performing a low-temperature oxidation process. a step of selectively converting the semiconductor layer that is not single crystallized into an oxide, or separating the single crystal semiconductor layer from the semiconductor layer that is not single crystallized, and adding an impurity of a conductivity type opposite to that of the substrate. A step of introducing an impurity having the same conductivity type as that of the substrate into at least a portion of the substrate below the single crystal semiconductor layer, and applying an energy beam irradiation with a long pulse width to form a single crystal A method for manufacturing a semiconductor device, comprising a step of forming a junction in a semiconductor substrate and a single crystal semiconductor layer.

Examples of the single crystal semiconductor substrate used in the present invention include single crystal silicon and single crystal germanium.

For the introduction of impurities in the present invention, it is desirable to adopt an ion implantation method that allows easy control of impurity introduction from the viewpoint of forming a shallow impurity introduction layer with high precision.

In the present invention, as a means for selectively opening holes in an insulating film portion adjacent to an impurity-introduced region, for example, impurities are introduced into a limited surface area of a semiconductor substrate using a photoresist pattern as a mask, and then the resist pattern is left as is. A method of dry etching using HF gas that can selectively remove the insulating film directly under the resist pattern in this state may be adopted. That is, by this method, openings in the insulating film are formed in self-alignment with respect to the impurity layer in the surface region of the semiconductor substrate.

Examples of the amorphous semiconductor layer used in the present invention include an amorphous silicon layer, an amorphous germanium layer, and the like. However, it is desirable that the amorphous semiconductor layer be made of the same material as the single crystal semiconductor substrate.

In the present invention, the energy beam, such as laser light, irradiated to the amorphous or polycrystalline semiconductor layer selectively melts only the amorphous or polycrystalline semiconductor layer, making it polycrystalline or single crystallized. It is necessary to use a short pulse width (μsec or less) in which the liquid phase phenomenon of the crystalline or polycrystalline semiconductor layer is dominant. For example, such a laser beam may have a wavelength of
Examples include Nd-YAG laser light of 1.06 μm and pulse width of 20 μsec.

In the present invention, a single crystal semiconductor layer is etched on a single crystal semiconductor substrate by irradiating an amorphous or polycrystalline semiconductor layer with a short pulse width laser beam, and a single crystal semiconductor layer is etched on an insulating film at a much higher etching rate than the above single crystal semiconductor layer. ,
It has the advantage that a polycrystalline semiconductor layer with a high oxidation rate can be formed. Therefore, by etching or low-temperature oxidation treatment, the polycrystalline semiconductor layer converted by the above treatment can be selectively etched away or converted into an oxide film, thereby achieving isolation and independence of the single crystal semiconductor layer.

In the present invention, an energy beam such as a laser beam irradiated after introducing impurities into a single crystal or polycrystalline semiconductor layer is used to form a crystal from the viewpoint of electrically activating impurities in a semiconductor substrate or a single crystal semiconductor layer to form a junction. It is necessary to use a pulse with a long pulse width (μsec or more) that can spread the solid phase phenomenon deep inside. Such a laser beam may have a wavelength of 0.696μ, for example.
Examples include ruby laser light with a pulse width of 1 msec and a pulse width of 1 msec.

Next, an example in which the present invention is applied to the manufacture of bipolar transistors will be described with reference to FIGS. 3a to 3g.

Example [] First, as shown in Figure 3a, the specific resistance is 18 to 25.
After partially diffusing arsenic into the surface region of the p ^- type silicon substrate 11 of Ω-cm to form an n ⁺ type buried layer 12 having a surface concentration of 10 ²⁰ cm ^-3 or more, the specific resistance becomes 0.2 Ω-. A single crystal n-type epitaxial layer 13 having a thickness of 1.5 μm and a thickness of 1.5 μm was grown. Next, as is well known, selective oxidation is performed using the Si ₃ N ₄ film as an oxidation-resistant mask, and the oxide film isolation region 1 is
After forming 4, 1000 ml in wet oxygen atmosphere.
℃ for 45 minutes to form a silicon oxide film 15 with a thickness of 3000 Å (as shown in FIG. 3A).

[] Next, the portion of the silicon oxide film 15 corresponding to the formation of the collector region is selectively etched to open a diffusion window, and thermal diffusion is performed at 1000°C for 20 minutes using PoCl ₃ as a diffusion source, ρs = 5Ω/□, depth 1.5 After forming the n ⁺ -type collector region 16 with a thickness of .mu.m, the entire surface of the silicon oxide film 15 was removed by etching, and thermal oxidation treatment was performed again at 1000.degree. C. for 25 minutes in a wet oxygen atmosphere. At this time, a silicon oxide film 17 with a thickness of 2000 Å is formed on the epitaxial layer 13 other than the collector region 16, and a silicon oxide film 17 with a thickness of 3500 Å is formed on the collector region 16.
A thick silicon oxide film 17' was grown (as shown in FIG. 3b).

[] Next, a resist film pattern 18 is provided on the silicon oxide film 17 by photolithography, and the resist film pattern 18 is used as a mask for outputting.
Boron was ion-implanted at 1.2×10 ¹⁵ cm ⁻² under the condition of 85 KeV to form an impurity region 19 serving as an external base (as shown in FIG. 3c). At this time, a thick silicon oxide film 1 of 3500 Å is formed on the collector region 16.
Because of the presence of 7', boron ions were hardly doped into the collector region 16 even without forming a resist film thereon.

[] Next, the resist film pattern 1 was exposed to CF ₄ plasma at a pressure of 1 Torr and 200 W for 1 minute.
After surface modification of the silicon oxide films 17, 17' exposed from 8, the silicon oxide films 17, 17' exposed from
Exposure to HF gas for 1 minute 20 seconds. At this time, the silicon oxide film 17 directly under the resist film pattern 18
The portion is selectively etched away to form the opening 2.
0 was formed. Subsequently, after removing the resist film pattern 18 with a mixed acid of H ₂ O ₂ and H ₂ SO ₄ ,
A 2000 Å thick amorphous silicon layer was deposited by vacuum evaporation. After that, wavelength 1.06μm, pulse width
200nsec, Nd-YAG with energy density 2J/ ^cm2
The entire surface was irradiated with laser light. At this time, the amorphous silicon layer is melted, and the amorphous silicon layer that is in contact with the single crystal n-type epitaxial layer 13 through the opening 20 is transferred to the single crystal silicon layer 21 and on the silicon oxide films 17 and 17'. The amorphous silicon layer was converted into a polycrystalline silicon layer 22 (as shown in FIG. 3d). In this case, the absorption coefficient of the single crystal n-type epitaxial layer 13 for short pulse width laser light is extremely low, so the laser effect is not as great as that of the epitaxial layer 13. Next, the entire surface was wet etched. At this time, the polycrystalline silicon layer 22
Since the etching rate was higher than that of the single crystal silicon layer 21, only the polycrystalline silicon layer 22 was selectively removed, leaving the single crystal silicon layer 21 in the opening 20 (as shown in FIG. 3e).

[] Next, boron ions were implanted at 1×10 ¹⁴ cm ^-2 on the entire surface under conditions of an output of 85 KeV, and the output was increased.
Arsenic ions were implanted at 3×10 ¹⁵ cm ⁻² under the condition of 100 KeV. At this time, boron ions are introduced into the surface region of the epitaxial layer 13 through the single crystal silicon layer 21, and arsenic ions are introduced into the surface region of the epitaxial layer 13 through the single crystal silicon layer 21.
It will be introduced in 1. Next, the wavelength is 0.696μm,
Ruby laser light with a pulse width of 1 msec and an energy density of 50 J/cm ² was irradiated. At this time, all of the ion-implanted layers are electrically activated while the implanted atoms remain in a state perpendicular to the implantation, and the impurity region 19 formed in the step [] described above is converted into the external base region 23. At the same time, the epitaxial layer 13 is formed through the single crystal silicon layer 21.
The boron implanted layer in the surface region forms the internal base region 24.
As a result, the base regions 23 and 24 are interconnected, and an emitter region 25 is formed in the single crystal silicon layer 21 (as shown in FIG. 3f).
Note that the p ⁺ type external base region 23, the p ⁺ type internal base region 24, and the n ⁺ type emitter region 25 have ρs and depths of 100 Ω/□, 0.4 μm, and 600 Ω/□, respectively.
0.45μm (base length 0.3μm), 25Ω/□, 0.15μm
It became.

[] After that, the silicon oxide film 17 on the p ⁺ type external base region 23 and the silicon oxide film 17' on the collector region 16 are selectively etched, and the base,
After making the contact hole for the collector, take out the base, collector, and emitter using the usual method.
A bipolar transistor was fabricated by forming Al electrodes 26, 27, and 28 (as shown in FIG. 3g).

In this example, the electrical activation of the ion-implanted layer is performed by laser irradiation, so the impurity distribution immediately after ion implantation is preserved.
The base length can be easily controlled, making process design easier. In addition, since the ion-implanted layer in the epitaxial layer 13 is activated by laser irradiation with a long pulse width to form an emitter-base junction, it is possible to prevent short-circuiting of the emitter-base junction when forming the emitter-extracting Al electrode 28. This can contribute to improving the yield of transistors, and by forming a shallow base and emitter, the epitaxial layer 13 can be made thinner and the isolation region can be made shallower. Furthermore, all the junctions are self-aligned and formed simultaneously, and the n ⁺ type emitter region 25
Since the p ⁺ -type external base region 23 does not come into contact with each other, a reduction in breakdown voltage can be suppressed, and the junction capacitance can be significantly reduced. As a result, it was possible to easily manufacture bipolar transistors with high integration and high speed.

Further, in addition to laser light, any energy beam such as an electron beam may be used, and by controlling the scanning speed, substantially short and long pulse irradiation can be achieved even with continuous wave irradiation.

As detailed above, according to the present invention, shallow junctions can be formed in self-alignment without high-temperature treatment, the length of the junction can be easily controlled, and short circuits between the junctions can be prevented when forming electrodes. It is possible to provide a method for manufacturing a semiconductor device with high reliability, high integration, and high speed at a high yield.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are cross-sectional views showing a part of a bipolar transistor manufactured by a conventional method, respectively;
3a to 3g are cross-sectional views showing the manufacturing process of a bipolar transistor in an embodiment of the present invention. 11...p-type silicon substrate, 12...n ⁺ buried layer, 13...single crystal n-type epitaxial layer, 14
...Oxide film isolation region, 16...Collector region, 1
7, 17'...Silicon oxide film, 18...Resist film pattern, 20...Opening portion, 21...Single crystal silicon layer, 22...Polycrystalline silicon layer, 23...
...p ⁺ type external base region, 24...p ⁺ type internal base region, 25...n ⁺ type emitter region, 26,2
7,28...Al electrode.

Claims (1)

[Claims] 1. After providing an insulating film on a single-crystal semiconductor substrate of one conductivity type, a step of introducing an impurity of a conductivity type opposite to that of the substrate into a surface region of the semiconductor substrate through a limited region of the insulating film; A process of selectively opening holes in the insulating film adjacent to this impurity-introduced region, and after depositing an amorphous or polycrystalline semiconductor layer on the entire surface, irradiation with a short pulse width energy beam is performed to open the insulating film. A step of monocrystallizing a portion of the amorphous or polycrystalline semiconductor layer that contacts the single crystal semiconductor substrate through the hole, and selectively removing the semiconductor layer that cannot be monocrystalized by etching or low-temperature oxidation treatment. selectively converting the semiconductor layer that is not single-crystallized into an oxide by performing a step of converting the semiconductor layer that is not single-crystallized into an oxide, or separating the single-crystal semiconductor layer from the semiconductor layer that is not single-crystallized, and having a conductivity type opposite to that of the substrate. Introducing impurities into at least a portion of the substrate below the single crystal semiconductor layer, and
A step of introducing an impurity of the same conductivity type as the substrate into a surface region of the single crystal semiconductor layer, and a step of forming a junction in the single crystal semiconductor substrate and the single crystal semiconductor layer by applying energy beam irradiation with a long pulse width. A method for manufacturing a semiconductor device, comprising: and. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is introduced by ion implantation. 3. The process of selectively opening holes in the insulating film adjacent to the impurity introduction region is performed by leaving the photoresist pattern used as a mask for forming a limited area of the insulating film when introducing the impurity into the semiconductor substrate, and using HF. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is carried out by selectively etching the insulating film directly under the resist pattern using a gas.