JPS6360593A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS6360593A JPS6360593A JP20621786A JP20621786A JPS6360593A JP S6360593 A JPS6360593 A JP S6360593A JP 20621786 A JP20621786 A JP 20621786A JP 20621786 A JP20621786 A JP 20621786A JP S6360593 A JPS6360593 A JP S6360593A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- hybrid integrated
- chip
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は混成集積回路装置に関し、特にその実装密度
を高めたものに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and particularly to one with increased packaging density.
第２図は従来の混成集積回路装置を示し、図において、
１は基板、２は該基板１上に搭載されたチップコンデン
サ、３は咳チップコンデンサ２同士を接続する導体であ
る。FIG. 2 shows a conventional hybrid integrated circuit device, and in the figure,
1 is a substrate, 2 is a chip capacitor mounted on the substrate 1, and 3 is a conductor connecting the chip capacitors 2 to each other.
このような混成集積回路装置では、所望する容量値がな
い時や容量値が大きい時、チップコンデンサ３を２ヶ以
上並列接続して基板１に搭載していた。In such a hybrid integrated circuit device, when a desired capacitance value is not available or when the capacitance value is large, two or more chip capacitors 3 are connected in parallel and mounted on the substrate 1.
従来の混成集積回路装置は以上のように構成されている
ので、チップ部品を実装する時、チップ部品を基板上に
通常平面的に配置するため、チップ部品を複数個並列接
続して基板上に搭載する場合、チップ部品の占有面積が
大きくなり、基板面積が増大するという問題点があった
この発明は上記のような問題点を解消するためになされ
たもので、基板面積の増大を招くことなく実装チップ数
を増加できる混成集積回路装置を得ることを目的とする
。Conventional hybrid integrated circuit devices are configured as described above, so when mounting chip components, the chip components are usually arranged flat on the board, so multiple chip components are connected in parallel and placed on the board. When mounted, there was a problem that the area occupied by the chip components became large and the board area increased.This invention was made to solve the above problems, and it does not cause an increase in the board area. An object of the present invention is to obtain a hybrid integrated circuit device that can increase the number of mounted chips without any problems.
この発明に係る混成集積回路装置は、複数のチップ部品
を垂直に積み重ねて実装してなるものである。A hybrid integrated circuit device according to the present invention is formed by vertically stacking and mounting a plurality of chip components.
この発明においては複数のチップ部品を垂直に積み重ね
て実装するようにしたから、一定の面積の基板に多くの
部品を実装できる。In this invention, since a plurality of chip components are vertically stacked and mounted, many components can be mounted on a board with a fixed area.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による混成集積回路装置を示
し、図において、１は基板、２ａは基板１上に搭載され
た下側のチップコンデンサ、２ｂは該下側チップコンデ
ンサ２ａ上に積み重ねて実装された上側チップコンデン
サである。FIG. 1 shows a hybrid integrated circuit device according to an embodiment of the present invention, in which 1 is a substrate, 2a is a lower chip capacitor mounted on the substrate 1, and 2b is a lower chip capacitor mounted on the lower chip capacitor 2a. This is an upper chip capacitor mounted in a stack.
ここでは、０，１μのチップコンデンサ２ａ、２ｂを２
階建てに積み重ねて０．２μの容量チップを得ており、
第１図のように実装する事により従来の場合（第２図）
に比べ実装面積は半分となり、基板の面積も小さくなり
、実装密度が高められる事になる。Here, 0.1μ chip capacitors 2a and 2b are connected to 2
The capacitance chips of 0.2 μ are obtained by stacking them in a story.
In the conventional case (Fig. 2) by implementing as shown in Fig. 1.
The mounting area is halved compared to the previous model, the board area is also smaller, and the mounting density is increased.
更に、３ヶ積み重ねると容量値が０．３μＦと大きくな
っても実装面積は変わらない為従来に比べ実装密度を大
きく上げることができる。Furthermore, when three devices are stacked, the mounting area remains the same even if the capacitance increases to 0.3 μF, making it possible to greatly increase the mounting density compared to the conventional method.
このように本実施例装置では２つのチップコンデンサを
並列接続する時下側チップコンデンサ２ａの上に上側チ
ップコンデンサ２ｂを垂直に積み重ねるようにしたので
、実装面積を増大させることなく、チップコンデンサ２
ｂを追加でき実装密度を高めることができる。In this way, in the device of this embodiment, when two chip capacitors are connected in parallel, the upper chip capacitor 2b is stacked vertically on the lower chip capacitor 2a.
b can be added and the packaging density can be increased.
以上のように本発明にかかる混成集積回路装置によれば
、複数のチップ部品を垂直に積み重ねて実装するように
したので、実装密度を上げ基板の面積を小さくでき、も
って、小形化、低コスト化を実現できる。As described above, according to the hybrid integrated circuit device according to the present invention, since a plurality of chip components are vertically stacked and mounted, the mounting density can be increased and the area of the board can be reduced, resulting in miniaturization and low cost. can be realized.
第１図は本発明の一実施例による混成集積回路装置を示
す斜視図、第２図は従来の混成集積回路装置を示す斜視
図である。
１・・・基板、２ａ・・・下側チップコンデンサ、２ｂ
・・・上側チップコンデンサ。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a perspective view showing a hybrid integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a perspective view showing a conventional hybrid integrated circuit device. 1... Board, 2a... Lower chip capacitor, 2b
...Upper chip capacitor. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
装してなることを特徴とする混成集積回路装置。(1) A hybrid integrated circuit device characterized by being formed by vertically stacking and mounting a plurality of chip components on a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20621786A JPS6360593A (en) | 1986-09-01 | 1986-09-01 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20621786A JPS6360593A (en) | 1986-09-01 | 1986-09-01 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6360593A true JPS6360593A (en) | 1988-03-16 |
Family
ID=16519706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20621786A Pending JPS6360593A (en) | 1986-09-01 | 1986-09-01 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6360593A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005072033A1 (en) * | 2004-01-27 | 2005-08-04 | Matsushita Electric Industrial Co., Ltd. | Circuit board and method for mounting chip component |
| JP2006123156A (en) * | 2004-11-01 | 2006-05-18 | K D K Kk | Rotary cutter and crimped paper leaf manufacturing apparatus for cut paper using the same |
-
1986
- 1986-09-01 JP JP20621786A patent/JPS6360593A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005072033A1 (en) * | 2004-01-27 | 2005-08-04 | Matsushita Electric Industrial Co., Ltd. | Circuit board and method for mounting chip component |
| US7667299B2 (en) | 2004-01-27 | 2010-02-23 | Panasonic Corporation | Circuit board and method for mounting chip component |
| JP2006123156A (en) * | 2004-11-01 | 2006-05-18 | K D K Kk | Rotary cutter and crimped paper leaf manufacturing apparatus for cut paper using the same |
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