JPS6360923B2 - - Google Patents
Info
- Publication number
- JPS6360923B2 JPS6360923B2 JP58083077A JP8307783A JPS6360923B2 JP S6360923 B2 JPS6360923 B2 JP S6360923B2 JP 58083077 A JP58083077 A JP 58083077A JP 8307783 A JP8307783 A JP 8307783A JP S6360923 B2 JPS6360923 B2 JP S6360923B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor chip
- input
- output
- metallized
- lead electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/601—Capacitive arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
- H10W44/226—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for HF amplifiers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Microwave Amplifiers (AREA)
Description
〔発明の属する技術分野〕
本発明は半導体装置にかかり、特に高周波トラ
ンジスタ、なかでも高周波高出力トランジスタに
関する。
〔従来技術〕
今日、高周波高出力トランジスタの発達は目を
見張るものがあり、動作周波数では数10GHzを越
え、出力レベルでは1000W近くのものも開発され
ている。ここで高周波トランジスタの動作周波数
レベルを向上させる為には、エミツタベース両接
合をできるだけ浅く形成し、ベース幅を極力狭く
して利得帯域幅積fTを高める必要があることは周
知の事実である。しかし動作周波数が高くなるに
つれて高出力トランジスタにおいては、原理的に
電力利得及びコレクタ効率といつた最も重要なパ
ラメータがそれに応じて低下する。この場合、さ
らに高出力化を計ろうとする為には、トランジス
タチツプ面積の増大は、取り扱いうる電流量や熱
放散の関係上当然必要となり、それに比例して接
合容量などの寄生素子が増えることは否めなくな
る。また、いくらトランジスタチツプのパターン
を微細にしても程度の差こそあれ上記の状況は避
けられなくなり、電力利得及びコレクタ効率の低
下とともに製造歩留の低下も問題となつてくる。
〔発明の目的〕
本発明は以上の問題点に対処してなされたもの
で、電力利得及びコレクタ効率の低下を防ぎ、か
つ製造歩留の低下を防止しうる高周波高出力トラ
ンジスタを提供するにある。
〔発明の構成〕
本第１の発明は、誘電体部材と該誘電体部材上
にそれぞれ設置された入力用、出力用及び接地用
金属化部分と、前記出力用金属化部分上に接着さ
れたトランジスタチツプとを有し、前記トランジ
スタチツプ上の入力用外部引き出し電極と前記入
力用金属化部分が、また前記トランジスタチツプ
上の接地用外部引き出し電極と前記接地用金属化
部分とがそれぞれ金属部材にて接続されている半
導体装置において、前記トランジスタチツプ上の
入力用外部引き出し電極と前記出力用金属化部分
とがそれぞれ金属部材にて接続されていることを
特徴とする半導体装置にある。
また、本第２の発明は誘電体部材と該誘電体部
材上にそれぞれ設置された入力用、出力用及び接
地用金属化部分と、前記出力用金属化部分上に接
着されたトランジスタチツプとを有し前記トラン
ジスタチツプ上の入力用外部引き出し電極と前記
入力用金属化部分が、また前記トランジスタチツ
プ上の接地用外部引き出し電極と前記接地用金属
化部分とがそれぞれ金属部材にて接続されている
半導体装置において、前記出力用金属化部分上に
容量性部材が接着されており、該許量性部材と前
記トランジスタチツプ上の入力用外部引き出し電
極とがそれぞれ金属部材にて接続されていること
を特徴とする半導体装置にある。
〔発明の原理と作用〕
本発明では、トランジスタチツプの入力側のボ
ンデイングパツドとトランジスタチツプが搭載さ
れている出力用メタライズ領域とをある適当な長
さを持つたボンデイングワイヤ等により接続する
ことによりボンデイングワイヤの持つているイン
ダクタンス成分により、トランジスタチツプが内
部的に持つている帰還容量成分を動作周波数にお
いて共振させキヤンセルすることにより高周波で
高出力高利得及び高コレクタ効率トランジスタを
実現したものである。
しかるにこの場合には直流的には入力出力間が
電気的に短絡することになるので、これを避ける
ためには、トランジスタチツプが搭載されている
出力用メタライズ領域上にトランジスタチツプと
は適当な関係位置を持つてできるだけ大きいキヤ
パシタンス分を持つたMOSコンデンサ又はセラ
ミツクコンデンサ等を搭載し、トランジスタチツ
プ上の入力側のボンデイングパツドと前記コンデ
ンサとをボンデイングワイヤ等で接続することで
目的を達成したものである。
また、本発明の場合は高周波化すればするほど
共振させるに必要なボンデイングワイヤの持つイ
ンダクタンス成分は小さくてよいため、ボンデイ
ングワイヤの長さが短くてよく、トランジスタの
形状がコンパクトにできる。また高出力化すれば
するほど、即ちトランジスタチツプが大きくなれ
ばなるほど、トランジスタチツプが持つている帰
還容量が大きくなるため、ある動作周波数におい
て、上記帰還容量をキヤンセルするに必要なイン
ダクタンス成分は小さくてよく、やはりトランジ
スタの形状が簡単になるという利点を有してい
る。
〔実施例〕
以下図面を参照し本発明の詳細につき説明す
る。第１図は本発明の一実施例による高周波高出
力トランジスタの概略図である。まず熱伝導性の
良いベリリア等の誘電体基板１上に入力用メタラ
イズ部分２、出力用メタライズ部分３及び接地用
メタライズ部分４が従来技術のメタライズ印刷等
により形成されている。この場合のメタライズ部
分の材質は金や銀等の貴金属が使用されるのが一
般的である。
さらに出力用メタライズ部分３上にはマウント
技術によりトランジスタチツプ５が接着されてい
る。そしてトランジスタチツプ５は入力用ボンデ
イングパツド５ａと接地用ボンデイングパツド５
ｂをそれぞれ有している。
さらに同じ出力用メタライズ部分３上には
MOSコンデンサまたはセラミツクコンデンサ等
容量性部材６もマウント技術により接着されてい
る。そこでトランジスタチツプ５上の入力用ボン
デイングパツド５ａボンデイングワイヤ７ａによ
り入力用メタライズ部分２と、またボンデイング
ワイヤ７ｃにより容量性部材６とそれぞれ接続さ
れてい。また接地用ボンデイングパツド５ｂは、
ボンデイングワイヤ７ｂにより接地用メタライズ
部分４と接続されている。ここにボンデイングワ
イヤ７ｃの持つインダクタンス分はほぼトランジ
スタチツプ５が内部的に持つ帰還容量をキヤンセ
ルできるように配慮されてトランジスタチツプ５
と容量性部材６とが出力用メタライズ部分３上に
配置されている。またこの場合、容量性部材６の
持つキヤパシタンスは可能な限り大きいのが好ま
しい。
また第２図は本発明の一実施例を示す第１図の
等価回路を示す。第２図中のL1，L2，L3はそれ
ぞれ第１図のボンデイングワイヤ７ａ，７ｂ，７
ｃのもつインダクタンス分を表わしている。また
第２図中のC1，C2はそれぞれ第１図のトランジ
スタチツプ５が内部的に持つている帰還容量分と
容量性部材６のキヤパシタンス分を表わしてい
る。
この場合ある動作周波数ｆにおいて近似的に
[Technical Field to Which the Invention Pertains] The present invention relates to semiconductor devices, and more particularly to high frequency transistors, particularly high frequency high output transistors. [Prior Art] Today, the development of high-frequency, high-output transistors is remarkable, with some having operating frequencies exceeding several tens of GHz and output levels approaching 1000 W. It is a well-known fact that in order to improve the operating frequency level of a high-frequency transistor, it is necessary to form the emitter-base junction as shallow as possible and to narrow the base width as much as possible to increase the gain-bandwidth product fT . However, as the operating frequency increases, the most important parameters in high-power transistors, such as power gain and collector efficiency, in principle, decrease accordingly. In this case, in order to achieve higher output, it is naturally necessary to increase the area of the transistor chip due to the amount of current that can be handled and heat dissipation, and the number of parasitic elements such as junction capacitance will increase proportionally. I can't deny it. Moreover, no matter how fine the pattern of the transistor chip is made, the above-mentioned situation is unavoidable to a greater or lesser extent, resulting in a problem of lowering the power gain and collector efficiency as well as lowering the manufacturing yield. [Object of the Invention] The present invention has been made to address the above problems, and an object of the present invention is to provide a high-frequency, high-output transistor that can prevent a decrease in power gain and collector efficiency, and can also prevent a decrease in manufacturing yield. . [Structure of the Invention] The first invention provides a dielectric member, a metallized portion for input, output, and grounding installed on the dielectric member, and a metallized portion for input, output, and ground bonded on the metallized portion for output. a transistor chip, and the external lead electrode for input on the transistor chip and the metallized part for input are each made of a metal member, and the external lead electrode for grounding on the transistor chip and the metallized part for ground are each made of a metal member. In the semiconductor device, the input external lead electrode on the transistor chip and the output metallized portion are each connected by a metal member. Further, the second invention includes a dielectric member, metallized parts for input, output, and grounding installed on the dielectric member, and a transistor chip bonded on the metallized part for output. The input external lead electrode on the transistor chip and the input metallized part are connected to each other by a metal member, and the ground external lead electrode on the transistor chip and the ground metallized part are connected to each other by a metal member. In the semiconductor device, a capacitive member is bonded on the output metallized portion, and the capacitive member and the input external lead electrode on the transistor chip are connected by a metal member, respectively. The semiconductor device is characterized by: [Principle and operation of the invention] In the present invention, the bonding pad on the input side of the transistor chip and the output metallized area on which the transistor chip is mounted are connected by a bonding wire or the like having a certain appropriate length. The inductance component of the bonding wire causes the internal feedback capacitance component of the transistor chip to resonate and cancel at the operating frequency, thereby realizing a transistor with high output, high gain, and high collector efficiency at high frequencies. However, in this case, there will be an electrical short circuit between the input and output in terms of direct current, so to avoid this, it is necessary to place an appropriate relationship between the transistor chip and the output metallized area on which the transistor chip is mounted. This purpose is achieved by installing a MOS capacitor or a ceramic capacitor, etc., which has as large a capacitance as possible given its position, and by connecting the bonding pad on the input side of the transistor chip to the capacitor using a bonding wire, etc. be. Further, in the case of the present invention, the higher the frequency, the smaller the inductance component of the bonding wire required for resonance, so the length of the bonding wire can be shortened, and the shape of the transistor can be made compact. Furthermore, the higher the output, that is, the larger the transistor chip, the larger the feedback capacitance of the transistor chip, so at a certain operating frequency, the inductance component required to cancel the feedback capacitance is small. This also has the advantage of simplifying the shape of the transistor. [Example] The present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic diagram of a high frequency, high power transistor according to an embodiment of the present invention. First, an input metallized portion 2, an output metallized portion 3, and a ground metallized portion 4 are formed on a dielectric substrate 1 made of beryllia or the like having good thermal conductivity by conventional metallization printing or the like. In this case, the material of the metallized portion is generally a noble metal such as gold or silver. Further, a transistor chip 5 is bonded onto the output metallized portion 3 by mounting technology. The transistor chip 5 is connected to an input bonding pad 5a and a grounding bonding pad 5.
b. Furthermore, on the same output metallized part 3,
A capacitive member 6 such as a MOS capacitor or a ceramic capacitor is also bonded by mounting technology. Therefore, the input bonding pad 5a on the transistor chip 5 is connected to the input metallized portion 2 by a bonding wire 7a, and is connected to the capacitive member 6 by a bonding wire 7c. In addition, the grounding bonding pad 5b is
It is connected to the grounding metallized portion 4 by a bonding wire 7b. Here, the inductance of the bonding wire 7c is designed to cancel the feedback capacitance that the transistor chip 5 has internally.
and a capacitive member 6 are arranged on the output metallized portion 3. Further, in this case, it is preferable that the capacitance of the capacitive member 6 is as large as possible. Further, FIG. 2 shows an equivalent circuit of FIG. 1 showing one embodiment of the present invention. L 1 , L 2 , and L 3 in FIG. 2 are bonding wires 7a, 7b, and 7 in FIG. 1, respectively.
It represents the inductance of c. Further, C 1 and C 2 in FIG. 2 represent the feedback capacitance internally held by the transistor chip 5 of FIG. 1 and the capacitance of the capacitive member 6, respectively. In this case, at a certain operating frequency f, approximately
以上説明したように本発明によれば、電力利得
及びコレクタ効率の低下を防ぎ、かつ製造歩留の
低下を防止し得る半導体装置特に高周波高出力ト
ランジスタが容易に得られる。
As described above, according to the present invention, it is possible to easily obtain a semiconductor device, particularly a high-frequency, high-output transistor, which can prevent a decrease in power gain and collector efficiency, and can prevent a decrease in manufacturing yield.
第１図は本発明の一実施例による半導体装置の
概略上面図、第２図は第１図に示す本発明の一実
施例の等価回路図を示す。
１……誘電体部材、２……入力用メタライズ部
分、３……出力用メタライズ部分、４……接地用
メタライズ部分、５……トランジスタチツプ、５
ａ……トランジスタチツプ上の入力用ボンデイン
グパツド、５ｂ……トランジスタチツプ上の接地
用ボンデイングパツド、６……容量性部材、７ａ
……入力用メタライズ部分とと入力用ボンデイン
グパツドを接続するボンデイングワイヤ、７ｂ…
…接地用メタライズ部分と接地用ボンデイングパ
ツドを接続するボンデイングワイヤ、７ｃ……入
力用ボンデイングパツドと容量性部材を接続する
ボンデイングワイヤ。
FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the embodiment of the present invention shown in FIG. DESCRIPTION OF SYMBOLS 1... Dielectric member, 2... Metallized part for input, 3... Metallized part for output, 4... Metallized part for grounding, 5... Transistor chip, 5
a...Input bonding pad on the transistor chip, 5b...Grounding bonding pad on the transistor chip, 6...Capacitive member, 7a
...Bonding wire, 7b, connecting the input metallized part and the input bonding pad...
...A bonding wire that connects the grounding metallized part and the grounding bonding pad, 7c...A bonding wire that connects the input bonding pad and the capacitive member.
Claims (1)
された入力用、出力用及び接地用金属化部分と、
前記出力用金属化部分上に接着されたトランジス
タチツプとを有し、前記トランジスタチツプ上の
入力用外部引き出し電極と前記入力用金属化部分
が、また前記トランジスタチツプ上の接地用外部
引き出し電極と前記接地用金属化部分とがそれぞ
れ金属部材にて接続されている半導体装置におい
て、前記トランジスタチツプ上の入力用外部引き
出し電極と前記出力用金属化部分とがそれぞれ金
属部材にて接続されていることを特徴とする半導
体装置。 ２ 誘電体部材と該誘電体部材上にそれぞれ設置
された入力用、出力用及び接地用金属化部分と、
前記出力用金属化部分上に接着されたトランジス
タチツプとを有し前記トランジスタチツプ上の入
力用外部引き出し電極と前記入力用金属化部分
が、また前記トランジスタチツプ上の接地用外部
引き出し電極と前記接地用金属化部分とがそれぞ
れ金属部材にて接続されている半導体装置におい
て、前記出力用金属化部分上に容量性部材が接着
されており、該容量性部材と前記トランジスタチ
ツプ上の入力用外部引き出し電極とがそれぞれ金
属部材にて接続されていることを特徴とする半導
体装置。[Claims] 1. A dielectric member and metallized parts for input, output, and grounding installed on the dielectric member, respectively;
a transistor chip bonded on the output metallization portion, and the input external lead electrode on the transistor chip and the input metallization portion are also bonded to the ground external lead electrode on the transistor chip and the input external lead electrode on the transistor chip. In a semiconductor device in which the grounding metallized portion is connected to each other by a metal member, the input external lead electrode on the transistor chip and the output metallized portion are each connected to each other by a metal member. Characteristic semiconductor devices. 2. A dielectric member and metallized parts for input, output, and grounding installed on the dielectric member, respectively;
a transistor chip bonded on the output metallization portion, and the input external lead electrode on the transistor chip and the input metallized portion are also connected to the ground external lead electrode on the transistor chip and the ground. In the semiconductor device, a capacitive member is bonded on the output metallized portion, and the capacitive member and the input external drawer on the transistor chip are connected to each other by a metal member. A semiconductor device characterized in that the electrodes are connected to each other by a metal member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58083077A JPS59208754A (en) | 1983-05-12 | 1983-05-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58083077A JPS59208754A (en) | 1983-05-12 | 1983-05-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59208754A JPS59208754A (en) | 1984-11-27 |
| JPS6360923B2 true JPS6360923B2 (en) | 1988-11-25 |
Family
ID=13792110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58083077A Granted JPS59208754A (en) | 1983-05-12 | 1983-05-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59208754A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0335430U (en) * | 1989-08-11 | 1991-04-08 |
-
1983
- 1983-05-12 JP JP58083077A patent/JPS59208754A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0335430U (en) * | 1989-08-11 | 1991-04-08 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59208754A (en) | 1984-11-27 |
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