JPS6361002U - - Google Patents
Info
- Publication number
- JPS6361002U JPS6361002U JP15415286U JP15415286U JPS6361002U JP S6361002 U JPS6361002 U JP S6361002U JP 15415286 U JP15415286 U JP 15415286U JP 15415286 U JP15415286 U JP 15415286U JP S6361002 U JPS6361002 U JP S6361002U
- Authority
- JP
- Japan
- Prior art keywords
- programmable logic
- logic controller
- numerical
- register
- numerical value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Description
第１図は本考案の一実施例を示す回路ブロツク
図、第２図は上記実施例に於ける論理回路の構成
及びその動作を説明するための図である。
１……プログラマブルロジツクコントローラ、
２……論理回路、ＤＳ１，ＤＳ２，ＤＳ３……１
６進３桁数値設定器、ＮＤ１，ＮＤ２，ＮＤ３，
ＮＤ４……１６進４桁数値表示器、ＤＯＯＯ〜Ｄ
ＦＦＦ，Ｚ……１６ビツトレジスタ。
FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram for explaining the configuration and operation of a logic circuit in the above embodiment. 1...Programmable logic controller,
2...Logic circuit, DS1, DS2, DS3...1
Hexadecimal 3-digit value setter, ND1, ND2, ND3,
ND4... Hexadecimal 4-digit numerical display, DOOO~D
FFF, Z...16-bit register.
Claims (1)
グラマブルロジツクコントローラと、このプログ
ラマブルロジツクコントローラの入力端子に接続
された数値設定器と、上記プログラマブルロジツ
クコントローラの出力端子に接続された数値表示
器と、上記プログラマブルロジツクコントローラ
の内部に設けられ、上記数値設定器より設定数値
に基づく信号を読取り、同信号より複数個のレジ
スタの中から特定のレジスタを選択し、同レジス
タに記憶されている数値に基づく上記数値表示器
に出力する論理回路とを具備していることを特徴
とするプロクラマブルロジツクコントローラのレ
ジスタ内容表示回路。 A programmable logic controller having a plurality of registers for storing numerical values, a numerical value setter connected to an input terminal of the programmable logic controller, and a numerical display connected to an output terminal of the programmable logic controller. , which is provided inside the programmable logic controller, reads a signal based on the set value from the numerical value setter, selects a specific register from among a plurality of registers based on the signal, and selects the numerical value stored in the register. A register content display circuit for a programmable logic controller, comprising: a logic circuit based on the above-mentioned numerical display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15415286U JPS6361002U (en) | 1986-10-07 | 1986-10-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15415286U JPS6361002U (en) | 1986-10-07 | 1986-10-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6361002U true JPS6361002U (en) | 1988-04-22 |
Family
ID=31073686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15415286U Pending JPS6361002U (en) | 1986-10-07 | 1986-10-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6361002U (en) |
-
1986
- 1986-10-07 JP JP15415286U patent/JPS6361002U/ja active Pending
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