JPH01116845U - - Google Patents
Info
- Publication number
- JPH01116845U JPH01116845U JP1155688U JP1155688U JPH01116845U JP H01116845 U JPH01116845 U JP H01116845U JP 1155688 U JP1155688 U JP 1155688U JP 1155688 U JP1155688 U JP 1155688U JP H01116845 U JPH01116845 U JP H01116845U
- Authority
- JP
- Japan
- Prior art keywords
- dma transfer
- channels
- dma
- lengths
- length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Bus Control (AREA)
Description
第１図は本考案の一実施例に係る回路構成を示
すブロツク図、第２図は同実施例のＲＡＭの内容
を示す図、第３図は同実施例のＲＯＭの内容を示
す図、第４図は同実施例の動作を説明するための
タイミングチヤートである。
１１…ＣＰＵ、１２ａおよび１２ｂ…Ｉ／Ｏポ
ート、１３…ＲＯＭ、１４…ＲＡＭ、１５…アド
レス／レングスカウンタ、１６…テーブルアドレ
スカウンタ、１７…セレクタ、１８…ＤＭＡシー
ケンサ。
FIG. 1 is a block diagram showing the circuit configuration according to an embodiment of the present invention, FIG. 2 is a diagram showing the contents of the RAM of the same embodiment, FIG. 3 is a diagram showing the contents of the ROM of the same embodiment, and FIG. FIG. 4 is a timing chart for explaining the operation of the same embodiment. 11... CPU, 12a and 12b... I/O port, 13... ROM, 14... RAM, 15... address/length counter, 16... table address counter, 17... selector, 18... DMA sequencer.
Claims (1)
ングスを格納するテーブルと、 このテーブルからＤＭＡ転送を行なうチヤネル
のＤＭＡ転送アドレスおよびレングスを読出す読
出し手段と、 上記テーブルから読出されたＤＭＡ転送アドレ
スおよびレングスをセツトし、ＤＭＡ転送に伴つ
て上記セツトしたＤＭＡ転送アドレスおよびレン
グスを更新制御する更新制御手段とを具備し、上
記各チヤネルのＤＭＡ転送を実行することを特徴
とするＤＭＡ制御装置。[Claims for Utility Model Registration] A table for storing DMA transfer addresses and lengths of a plurality of channels; reading means for reading DMA transfer addresses and lengths of channels that perform DMA transfer from this table; A DMA control characterized by comprising an update control means for setting a DMA transfer address and length and updating the set DMA transfer address and length in conjunction with DMA transfer, and executing DMA transfer for each of the channels. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1155688U JPH01116845U (en) | 1988-01-30 | 1988-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1155688U JPH01116845U (en) | 1988-01-30 | 1988-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01116845U true JPH01116845U (en) | 1989-08-07 |
Family
ID=31220214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1155688U Pending JPH01116845U (en) | 1988-01-30 | 1988-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01116845U (en) |
-
1988
- 1988-01-30 JP JP1155688U patent/JPH01116845U/ja active Pending
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