JPS6364143A - Memory access control circuit - Google Patents

Abstract

PURPOSE:To detect the generation at a quick timing and to attain re-trial at an original memory access requester when a bank conflict occurs by providing a memory control circuit, an instruction decoding circuit, an instruction address control circuit, etc. CONSTITUTION:A memory control circuit 200 receives 0-type and 1-type access request signals from an instruction decoding circuit 100 and an instruction address control circuit 300 and accesses them to a memory bank A10 and a memory bank B20 in accordance with respective addresses. The circuit 100 and the circuit 300 execute the access request to the memory of the same bank simultaneously and when a bank conflict occurs, the processing is executed in accordance with the priority determined beforehand. The circuit 200 sends a 0-type address 110, etc., to the circuit 300, sends a 1-type address 310, etc., to the circuit 100 and exchanges the address, etc. Thus, the circuit 100 and the circuit 300 can know whether or not the access request is completed, the access requester detects the generation of the conflict at a quick timing and the re-trial can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control circuit, and particularly to a control circuit suitable for high-speed memory access.

[Conventional technology]

In conventional devices, memory is divided into multiple banks;
It was configured as a continuous address space. (For example, see Nikkei Electronics Book, General Purpose Large Computer J pp. 251-263 (May 1982)) To enable high-speed access as a memory access method, when an access requester sends a request, a request acceptance signal is sent from the memory control circuit. A method has also been proposed in which the next request is sent before the next request is received.If there is a delay at this time and the expected acceptance signal is not received, a retry will occur, and the requests after the failed request will be sent to the memory again. has been accessed again.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into consideration the case where the memory is divided into multiple banks, there are multiple memory access request sources, and multiple memory access requests may occur at the same time. There is a problem in that memory access requests that occur simultaneously can access the same bank, resulting in a new bank conflict. The problem with bank conflicts is that there are access requests that cannot access memory.

If this is not retried as soon as possible to complete the access, processing will be delayed and performance will deteriorate.

An object of the present invention is to detect the occurrence of a bank conflict at an early timing at the source of the memory access request and to retry the bank conflict.

[Means for solving problems]

The above object includes an exchange means for mutually exchanging memory access types, bank information, etc. between a plurality of memory access request sources, and a means for detecting occurrence of bank conflict based on the exchanged information and information of the memory access request sources; This is achieved by providing a means to retry based on the result.

[Effect]

The occurrence of a bank conflict is detected based on the memory access notified by the above exchange means and the information of the memory access request source, and a retry is performed based on the result. Compared to a method that waits until it is known before retrying, the timing for starting retrying is faster.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows the processor and main memory.

The main memory is composed of a puncture A memory 10 and a bank B memory 20, and depending on whether the address is an even number or an odd number, the bank B memory 20... Bank A memory 10 is selected.

The processor has a memory control circuit (SC) that controls the main memory.
tJ) 200, an instruction decoding circuit (IB) 100 that decodes instructions, calculates operand addresses, starts operand fetching, etc., an arithmetic circuit 30 that performs operations specified in the instruction, and manages the address of the next instruction to be executed. An instruction address management circuit CI that starts instruction fetch, etc.
A) It is roughly divided into 300 four circuits.

The arithmetic circuit 3o receives operand data from the memory control circuit 200 via the operand data bus 212, and performs an operation instructed by the instruction decoding circuit 100.When storing the operation result in the memory, it sends the store data to the store data bus 32, and stores the store request 34. Issue.

The instruction decoding circuit (IB) 100 decodes the instruction sent from the instruction data bus 116, calculates the operand address if there is an operand fetch request, and sends the address to the O-system address bus 110 for 0-system access. Request 1
Issue 12. In the 0-system access request, a branch destination instruction is also fetched.

The instruction address management circuit (IA) 300 manages the address of the next instruction, and sends out a fetch request for the next instruction using the 1-system address bus 310 and the 1-system access request 112. In the 1-system access request, an operand store for a store request sent from the arithmetic circuit 30 is also performed.

The memory control circuit (SCU) 200 receives access requests from the O system and 1 system, and assigns these access requests to their addresses and accordingly the puncture A.
Memory 10. The bank B memory 20 is accessed. O type if access is successful.

The 0 system corresponds to the 1 system access request 112,312.

1 system access acceptance signal 114.314 respectively 1B1
00. Send to lA300. Also, depending on whether the fetch is an operand fetch or an instruction fetch, the operand data bus 212. Operands or instructions are sent to the instruction data bus 116 together with transfer end signals 210 and 113, respectively.

If the access is not successful, no access acceptance signal is issued, whereby the IB100°1A300 detects that the access request has not been accepted and resends the access request. This operation is called redo.

One of the cases in which the accesses are not successful is when accesses of the O system and the 1 system that occur simultaneously are made to the same bank (for example, bank A memory 10).In this case, both requests cannot be completed. This is called a bank conflict.

When a bank conflict occurs, the 5CU 200 accepts the access with a higher continuous light order according to a predetermined priority order, and does not accept the others (here, the 0 system access is given priority). Therefore, the 1 system access becomes redundant.

0 system address 110.0 system access request 112゜0 system access reception 114 to lA300, 1 system address 310
．． The 1-system access request 312.1-system access reception 314 is sent to the IB 100.

This results in 1B100. The IA 300 can know whether or not mutual access is performed, and if so, to which memory bank.

Based on this information, 1JIB100. lA300 is 5CU
It is possible to detect in advance that the own access request is determined to be redo in 200, and as a result, 5CU200
Redo can be performed by waiting to confirm that no access acceptance signal is issued.

This operation will now be explained in terms of time with reference to FIG.

Figure 2 (a) shows the case where redo is performed after waiting for the redo judgment made in SCU, and Fig. 2 (b) shows the case where redo is performed without waiting for the redo judgment made in SCU and the redo is judged in IA. Indicates when to do so.

Here, it is assumed that the IMO is necessary for transmitting and determining signals to the four circuit parts of the processor that have been broadly classified above.

First, in the case of FIG. 2(a), the system 1 access request 312
are 1, 2, 3 in order. . . . is sent from the IA 300, and the 5CU 200 issues a 1-system access acceptance signal 314 if the 1-system access request 312 is acceptable. In this example, the 5CU 200 determines that the system 1 access request signal 312 issued at Ta and indicated by "3" cannot be accepted.
The system 1 access acceptance signal 314 is not issued from T4 (indicated by "(3)").

In response to this, the lA 200 issues a system 1 access request signal 312 indicated by "3" from Ta and performs a redo operation.
During this time, two cycles are left vacant.

Next, FIG. 2(b) will be explained. Here, the 0-system access request signal 112, etc. and the 1-system access request signal 312, etc. are exchanged between the lA300 and lB100 (7), respectively.
ItA"uB" in the figure is bank A memory 1, respectively.
0. Ta indicating an access request to bank B memory 20
Accesses issued in the bank create bank conflicts,
In both cases, an access request to bank B memory 20 has been issued. Since information such as the O-system access request 112 is detected in the IA 300, it is possible to predict that the request "3" will be determined as a redo by the 5CU 200 according to a predetermined priority order. Therefore l
A300 sends “ from T4 to system 1 access request signal 312.
3'' request can be issued by redo. During this time, only one idle cycle occurs, which is an improvement of one cycle compared to the example shown in FIG. 2(a).

As a result, the recovery operation from the conflict can be performed quickly, and the present discovery has the effect of equivalently increasing the memory throughput.

Next, FIG. 3 shows the configuration and operation of the lA300 that performs the above functions.The latches 320 and 330 are
lB100 to Lz. lA300 (7) Shows the type of access request issued and the memory bank, 0 system address 110.0 system access request 112, O system address reception 1
14, 1 system access request 312.1 system address 310
Updated by. Redo determination circuit 340 receives this information through signal lines 322 and 332, detects a bank conflict, determines whether or not to perform IA determination redo, and sends signal 342.

The memory access request determination circuit 350 receives a signal 36 from a latch 360 that stores the request that the lA 300 should originally issue.
2 and 1 system access acceptance signal 314 and signal 342 are received,
The next 1-system access request 312 is determined. Furthermore, it sends out a signal 314 that controls selectors 372 and 392 that select the address to be sent.

FIG. 4 shows the configuration of the 5CU 200.

The bank conflict determination circuit 220 uses the O system address 1i.
0. O system access request 112.1 system address 310.1
Upon receiving the system access request 312, occurrence of bank conflict is detected. If detected, 0 system access reception 114 according to a predetermined priority (here, 0 system priority)
is sent, and the 1st system access reception 314 is not sent.

If the access requests sent at the same time do not cause a bank conflict, each request is sent to the selector 230, 2
32 to address 12.22, and memory access is performed.

〔Effect of the invention〕

According to the present invention, request signals issued from a memory access request source are mutually exchanged among a plurality of request sources, and when a bank conflict occurs, each request source determines whether the request has been completed or not according to a predetermined priority order. Since this can be determined without waiting for the determination by the memory control circuit, the timing for reissuing a request can be made earlier if a bank conflict occurs.

This allows quick recovery from conflicts, which has the effect of equivalently increasing memory throughput.

[Brief Description of the Drawings] Fig. 1 is an overall configuration diagram of an embodiment of the present invention, Fig. 2 is a time chart showing memory access according to an embodiment of the present invention, and Fig. 3 is an instruction address of Fig. 1. An internal configuration diagram of the management circuit 300, FIG. 4 is an internal configuration diagram of the memory control circuit 200 of FIG. 10...Memory bank A, 20...Memory bank B
, 200...Memory control circuit, 300...Address management circuit, 100...Instruction decoding circuit, 340...Redo determination circuit, 350...Memory access request determination circuit, (-/' (b) IA judgment glue F 4th tail

Claims (1)

[Scope of Claims] 1. In a computer system having a plurality of access request circuits, a memory divided into banks, and a memory control circuit, the two access request circuits each having the memory control circuit 2, A means for exchanging memory access addresses from the access request circuits between the access request circuits, a latch provided for each access request circuit that stores access addresses sent in the past from other access request circuits, and each access request circuit. A memory access control circuit comprising a circuit that compares a memory access address newly generated in the circuit with the contents of the latch to determine whether a bank conflict has occurred.