JPS63643A - Program debugging system - Google Patents

Abstract

PURPOSE:To easily execute debugging by storing only a data in a trace point of subroutine of some condition, by setting a trace start address, and storing a data in a trace point of a subroutine after an instruction of its trace start address has been executed. CONSTITUTION:In a subroutine program after a trace start address which has been set to a register 4, and a program memory address have coincided, a data at the time when its trace point address and the program memory address have coincided is stored in a memory 3. Also, a subroutine return instruction, the data of the trace point is not stored until the trace start address and the program memory address coincide again. In this way, only the data in the timing in which monitoring is desired can be stored, therefore, debugging can be executed easily.

Description

[Detailed Description of the Invention] [Summary] A trace start address is set, and data at a trace point of a subroutine after the instruction at the trace start address is executed is stored. This makes debugging easier by storing only the data that is available.

[Industrial application field]

The present invention relates to a program debugging method for debugging a program by storing trace point data in subroutines.

It is possible to store data at specific points in time during program execution and debug the program based on that data. In this case, it is desired to be able to obtain trace data that is easy to distinguish.

[Conventional technology]

A conventional program debugging method in which trace data is stored and debugging is performed based on the data has been carried out using, for example, the configuration shown in FIG. In the same figure,
31 is a signal processing processor, 32 is a program memory,
33 is a memory for storing trace data, 35 is a register for setting a trace point address, 36 is a comparison circuit that compares the program memory address and the trace point address, 37 is a delay circuit, 38 is an address counter, and 39 is an inverter. .

The trace point TPO address of the program memory 32 is set in the register 35, and the signal processing processor 31
The address from is added to the address terminal ADH of the program memory 32, the data is transferred from the data terminal DATA to the signal processing processor 31, and processing is executed according to the decoding result. The program memory address in that case is applied to the comparison circuit 36 and compared with the trace point address set in the register 35, and if they match, a match signal via the delay circuit 37 is sent to the signal processor 31 to output the data bus. added as signal DBO,
added to the address counter 38 as a step clock;
It is also inverted by an inverter 39 and applied as a write enable signal *WE to the memory 33.

The data bus out circuit of the signal processing processor 31 has the configuration shown in FIG. 45 is in operation state,
The data on the internal data bus DBUS is transferred to the AND circuit 41.
It is output to external data bus EBUS via OR circuit 44 and gate circuit 45. At that time, external output register E
Data from OREG is inhibited by inhibit circuit 42. That is, when the data bus out signal DBO is applied to the signal processing processor 31, the data on the internal data bus DBUS from the internal register etc. is transferred to the external data bus EBU.
Output to S.

FIG. 8 shows a timing chart, (al is the program counter clock, (b) is the program memory address, (C1 is the data successively output from the program memory 31, (d) is the data set in the instruction register, (
el is the data on the internal data bus DBUS, (fl is the match signal from the comparison circuit 36, (g) is the data bus out signal DBO1 (hl is the data on the external data bus EBUS,
(1) indicates the address of the memory 33, and (J) indicates the write enable signal *wE applied to the memory 33.

According to the program counter clock shown in (a),
The address of the program memory 32 increments in the order of AO, AI, A2, . . . as shown in (bl).

With this program memory address, data DO, DI, D2 . . . . are output one after another and are sent to the instruction register in the signal processing processor 31 as shown in (d).

Program memory address A1 as trace point TP
Assuming that the address is , as shown in ffl, the comparator circuit 3
A match signal from 6 is output. This match signal is delayed by the delay circuit 37 and becomes the data bus out signal DBO shown in fg).

The data D1 sent to the instruction register is a transfer command, and the transfer data is output to the internal data bus DBUS as shown in tel, and is output to the internal data bus DBUS as shown in (gl). Then, the data is output to the external data bus EBUS.

Further, the address counter 38 counts up the coincidence signal passed through the delay circuit 37, and increments the address of the memory 33 from TAO to TAI, as shown in (1). With this address TAI and the rise of the write enable signal *WE, the trace data TD output to the external data bus EBUS is stored in the memory 33, and the next time it passes through the trace point again, it is stored at the address TA2 of the memory 33. Trace data will be stored.

[Problem to be solved by the invention] Conventional trace data is always stored no matter what conditions the trace point TP is passed through, and especially when the trace point TP is set in a subroutine program, Even in the case of a conditional subroutine call, trace data will be stored.

Therefore, debugging must be performed by making conditional judgments such as identifying subroutine calls, which has the disadvantage that debugging is not easy.

SUMMARY OF THE INVENTION An object of the present invention is to facilitate debugging by making it possible to store only the data of trace points set in a subroutine program with the following conditions.

[Means for solving problems]

The program debugging method of the present invention sets a trace start address, stores the trace point data after passing through this trace start address, and uses a subroutine return instruction to store the trace point data until the trace start address is passed again. This will be explained with reference to FIG. 1.

processor l and the program memory address PRA from processor 1 is applied to address terminal ADR;
a program memory 2 from which data is read from a data terminal DATA; a trace data store memory 3 which stores data output to an external data bus EBUS;
It includes a register 4.10, a return instruction decoder 5, a comparison circuit 6, a delay circuit 7, an address counter 8, and an inverter 9. The trace start address is set in the register 4, and the subroutine program trace is set in the register 10. Set the address of point TP.

The program memory address PRA and the trace start address set in the register 4 are compared in the comparison circuit 6, and after the comparison, the program memory address PRA is
A and the trace point address set in the register 10 are compared in the comparison circuit 6. When a match signal is obtained as a result of this comparison, the address counter 8 is incremented, the data bus out signal DBO is applied to the program 1, and the write enable signal *WE is applied to the memory 3, so that the processor The data on the internal data bus 1 is output to the external data bus EBUS, and the data is transferred to the memory 3.
Stored in

After the data at the trace point TP of the subroutine is stored in the memory 3, when the return instruction of the subroutine is decoded by the decoder 5, the trace point in the subroutine is stored until the trace start address and the program memory address PRA match again. I-TPO
This prohibits data storage. This prohibition is performed by controlling the comparison circuit 6 so that the trace point address set in the register 10 and the program memory address PRA are not compared, or by
Control is performed to prevent the output of the signal.

[Effect]

By setting the trace start address in register 4 in advance as the program memory address to be passed under the desired conditions, the data at that point will not be stored even if the trace point is passed under other conditions. . Also, when the subroutine return instruction is decoded, it returns to the initial state, and the trace point data is not stored until the trace start address and program memory address match again, so the subroutine when the conditions are satisfied Only tracepoint data from calls can be stored.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, which will be described below as snapshot processing. In the figure, 11 is a snapshot start register (SSR), 12 is a snapshot point register (SPR), I3 is a selector, 14 is a comparison circuit,
15, 23.30 are D flip-flops, 16.24 are R-S flip-flops, 17 is an AND circuit, 18 is a delay circuit, 19 to 21 are invert NOR circuits, 22 is an address counter, 25 is an inverter, 26 is a selector ,2
7 is a memory for storing trace data, 28 is an invert NOR circuit, 29 is a return instruction decoder, and the processor and program memory are not shown.

Corresponding to the configuration in FIG. 1, the memory 3 corresponds to the memory 27, the register 4 corresponds to the snare knob shot start register 11, the register 10 corresponds to the snapshot point register 12, and the comparison circuit 6 corresponds to the comparison circuit 6. The return instruction decoder 5 corresponds to the return instruction decoder 29, the address counter 8 corresponds to the address counter 22, and the delay circuit 7 corresponds to the delay circuit 18.

A snap shot start address is set in the snap shot start register 11, and a snapshot point address is set in the snap shot point register 12. Selector 13, flip-flop 1
When the Q terminal of 6 is "O", the G selects the snapshot start register 11 side, and when it is 1'', the snapshot point register 12 side is selected.

A program memory address PRA from a processor (not shown) is applied to the comparison circuit 14 and also to a program memory (not shown), and a program counter clock PCGK is applied to the flip-flop 15.2.
Clock terminal C of 3 and clock terminal GK of delay circuit 1B
added to. 5SSF is a flag that is set to “1” before snapshot execution, and
is a reset signal.

The address from the address counter 22 or the successive address from the processor is added to the address terminal ADR of the memory 27 via the selector 26, and the inverter 25
The write enable signal *WE of the output signal of is applied, and the data applied to the data terminal DATA via the external data bus EBUS is written into the memory 27.

In response to the reset signal XR3T, a clear signal is applied to the clear terminal CLR of the address counter 22, and the address counter 22 is cleared to the initial state.

Also, the Q terminal output signal of the flip-flop 16 is applied to the inhibit input terminal IN H of the return instruction decoder 29,
When the Q terminal output signal is "1", the return instruction decoder 29 becomes active, and when the subroutine return instruction RTN is decoded, the flip-flop knob 30 is set by the decoded output signal, thereby resetting the flip-flop 16. be done.

FIG. 3 shows a timing chart of an embodiment of the present invention,
(a) to (11) show an example of the signal a%i of each part in FIG. 2, and (J) shows another example of the signal d. The operation of the diagram will be explained.

In normal program memory access, the program counter clock a (PCCK) shown in (&)
A program counter (not shown) counts up the program memory address b (P
RA) is AO, AI, A2. A3. It is progressed as follows. Assuming that the snapshot start address is SA and the snapshot point address in the subroutine program is PA, the snapshot start address SA is set in the register 11 and the snapshot point address PA is set in the register 12.

In this state, the Q terminal output of the clip-flop 16 is “
0'', and the Q terminal output of the flip-flop 24 is 0', so the selector 13 selects the register 1 side and adds the snapshot start address SA to the comparison circuit 14, and the comparison circuit 14 is in the operating state and the return instruction decoder 29 is in a stopped state. In this state, the program memory address b (PRA) is compared with the snapshot start address SA in the comparison circuit 14, and the subroutine call under the condition or the address A1 immediately before it is set as the snapshot start address. Assuming SA, 5A=AI. As shown in (e), a match signal e is output, and this match signal e is applied to the data terminal of the flip-flop 15 and the AND circuit 17.

When flip-flop 15 is set by the next program counter clock a, flip-flop 16
is also set, and the Q terminal output signal C becomes "1" as shown in fc), entering the snapshot mode. Then, the inhibit input terminal I N of the return instruction decoder 29
When 1'' is added to H, the operating state is entered.

The Q terminal output signal C of the flip-flop 16 is applied as a count enable signal to the enable terminal EN of the address counter 22, and counts up the data bus out signal f (DBO) applied to the clock terminal CK. Also, at this point, the Q terminal output signal d of the flip-flop 24 is "0" as shown by +d), and the comparator circuit 14 continues to be in the operating state.

Then, by entering the snapshot mode, the selector 13 selects the register 12 side and adds it to the comparison circuit 14, so the program memory address b (PRA
) and the snapshot point address are compared in the comparison circuit 14.

When the program memory address b (PRA) is incremented and becomes A4=PA, the comparison circuit 14 outputs a match signal e as shown in (el). Since the output signal is 1'', it is applied to the delay circuit 18 via the AND circuit 17.

The delay circuit 18 delays the coincidence signal e in synchronization with the program counter clock a (PCCK) applied to the clock terminal CK, and is composed of a shift register or the like.

The output signal f shown in (f) of this delay circuit 18 becomes the data bus out signal DBO, and is applied to the processor, the clock terminal GK of the address counter 22, and the memory 27 via the inverter 25. Added as write enable signal *WE. The address signal g from the address counter 22 is T as shown in (g).
Steps from AO to TAI, this address signal g is applied to the address terminal ADH of the memory 27 via the selector 26, and the data h shown in (h) output from the processor to the external data bus EBUS is written to the memory 27. be included.

Next, if the subroutine return instruction RTN is read out to program memory address b (PRA) 86, the subroutine return instruction RTN is decoded by the return instruction decoder 29, and the decoded output signal is sent to the data terminal of the flip-flop 30. Since the next program counter clock a (PC
CK), the flip-flop 30 is set, and its d-terminal output signal becomes 60°. This resets flip-flop 16 and exits the snapshot mode.

After reaching the program memory address PRA that matches the snapshot start address, the snapshot point address and program memory address PRA are
When the data bus out signal DBO is applied to the processor, the processor outputs the external data bus EB.
The data output to US is written into memory 27.

The address counter 22 sequentially outputs the data bus out signal DB.
When O is counted up and a carrier signal i is output as shown in (1), data has been written to the capacity of the memory 27. Therefore, the flip-flop 23 is set by this carrier signal i, which sets the flip-flop 24, and its Q.
Since the terminal output signal d becomes "1" as shown in 01,
The operation of the comparator circuit 14 is stopped and the snapshot prohibition mode is entered.

Since the d-terminal output signal of the flip-flop 24 that has been set becomes "0", the output signal of the invert NOR circuit 21 becomes "0", the flip-flops 15 and 16 are reset, and the delay circuit 18 is cleared. Therefore, The data stored in the memory 27 will not be overwritten. Then, when successive addresses from the processor are added to the memory 27 via the selector 26, the data is read from the data terminal DATA and output to the external data bus EBUS. be done.

FIG. 4 is an explanatory diagram of the program, in which the subroutine call (■) in the main program causes the transition to the subroutine program as shown by the solid line arrow, and the subroutine return instruction RTN returns to the main program as shown by the solid line arrow. become. In addition, in the case of the subroutine call (■), as shown by the dotted arrow, the transition is made to the subroutine program, and the subroutine return command RT is executed.
By N, the program returns to the main program, by subroutine call (3), it moves to the subroutine program as shown by the chain arrow, and by subroutine return command RTN, it returns to the main program.

Set the snapshot start address SA at or immediately before the subroutine call address in ■, and set the snapshot point address P during the subroutine program.
If A is set, this snapshot start address SA is set in the register 11, and the snapshot point address PA is set in the register 12.

Even if the subroutine program is executed according to the subroutine call in ■ and passes the snapshot start address PA,
Since the comparison circuit 14 does not compare the program memory address PFIA with the snapshot point address PA set in the register 12, the data at that point is not stored in the memory 27. .

When the snapshot start address SA is passed, the match signal e from the comparison circuit 14 causes the flip-flop 15 to be activated.
．． 16 cents and enters snapshot mode,
When the subroutine program is entered by the subroutine call (2) and the snapshot point address PA is reached, the match signal e from the comparison circuit 14 is output, the data bus out signal DBO is applied to the processor via the delay circuit 18, and The address of memory 27 is incremented, a write enable signal *WE is applied to memory 27, and the data at the snapshot point is output from the processor to external data bus EBUS and written to memory 27.

The subroutine return instruction RTN returns to the main program, but if the subroutine return instruction RTN is not decoded by the decoder 29, the following
When the subroutine program is entered by the subroutine call and the snapshot point address PA is passed, the data at that time is stored in the memory 27.

Therefore, the data stored in the memory 27 is as shown in (al) in FIG.
indicates the data of snapshot point address PA by subroutine calls ■, ■, and i (1, 2
, 3, . . . ) corresponds to the number of times the main program is repeated by jump start. In this case, it is difficult to identify whether the data is the snapshot point data due to the subroutine call (2) or the data at the snapshot point due to the subroutine call (2).

Therefore, when transitioning to the subroutine program by the subroutine call in (■), the snapshot mode is entered and the subroutine return instruction RTN is sent to the decoder 2.
9, the decoded output signal sets the flip-flop 30, thereby resetting the flip-flop 16, and the next subroutine call (2) moves to the subroutine program, even if it becomes the snapshot point address PA. This prevents current data from being stored in the memory 27.

In this way, by controlling the snapshot mode to return to its original state using the subroutine return instruction RTN, the data stored in the memory 27 is stored in (b) of FIG.
). That is, only the data at the snapshot point when transitioning to the subroutine program by the subroutine call in 2) is stored. Furthermore, if the snapshot start address SA is set to the subroutine call (2), it will be stored in the snap shot pointer 27 when the subroutine program is transitioned to by the subroutine call (2). Therefore, debugging is facilitated because it can be determined which subroutine call was used to determine which snapshot point data was transferred.

The present invention is not limited to the configuration of the above-described embodiment, but can employ various logical configurations.

(Effects of the Invention) As explained above, the present invention allows the trace point address and the program memory address to be matched in the subroutine program after the trace start address set in the register 4 and the program memory address match. The data at the time of a match is stored in the memory 3, and the trace point data is not stored until the trace start address and the program memory address match again by a subroutine return instruction.
Since only data at the timing desired to be monitored can be stored, there is an advantage that debugging is facilitated.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a timing chart of an embodiment of the invention, Fig. 4 is an explanatory diagram of the program, and Fig. 5 ( a
), (bl is an explanatory diagram of trace data, FIG. 6 is an explanatory diagram of a conventional example, FIG. 7 is a data bus out circuit, and FIG. 8 is a timing chart of a conventional example. l is a processor, and 2 is a program memory. , 3 is a trace data store memory, 4 is a register, 5 is a return instruction decoder, 6 is a comparison circuit, 7 is a delay circuit, 8 is an address counter, 10 is a register, 11 is a snapshot start register, 12 is a snapshot point Register, 13 is selector, 14 is comparison circuit, 15, 23.3
0 is a D flip-flop, 16.24 is an R-S flip-flop, 17 is an AND circuit, 18 is a delay circuit, 19-
21 and 28 are invert NOR circuits, 22 is an address counter, 26 is a selector, 27 is a memory, and 29 is a return instruction decoder.

Claims (1)

[Claims] A program debugging method comprising a processor (1), a program memory (2), and a memory (3) for storing trace data, and storing data at a trace point in the memory (3). A register (4) for setting a trace start address and a subroutine return instruction decoder (5) are provided, and the data of the trace point of the subroutine after the trace start address and the program memory address match are stored in the memory ( 3) and after decoding the subroutine return instruction by the subroutine return instruction decoder (5), prohibiting the storage of data at the trace point until the trace start address and program memory address match again. A program debugging method featuring: