JPS6364407A - Emitsuta follower circuit - Google Patents

Emitsuta follower circuit

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Publication number
JPS6364407A
JPS6364407A JP20784886A JP20784886A JPS6364407A JP S6364407 A JPS6364407 A JP S6364407A JP 20784886 A JP20784886 A JP 20784886A JP 20784886 A JP20784886 A JP 20784886A JP S6364407 A JPS6364407 A JP S6364407A
Authority
JP
Japan
Prior art keywords
transistor
constant voltage
potential
output terminal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20784886A
Other languages
Japanese (ja)
Inventor
Tomoaki Hirai
智明 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP20784886A priority Critical patent/JPS6364407A/en
Publication of JPS6364407A publication Critical patent/JPS6364407A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To keep high input resistance and protect a constant current source transistor by providing a clamping circuit that restrict collector potential of the constant current source transistor to the output terminal of an emitter follower circuit. CONSTITUTION:A transistor 6 in which the base is connected to the constant voltage point 23 of a constant voltage circuit 25, the collector is connected to a DC power source 30 and the emitter is connected to an output terminal 50 is provided. When signals to an input terminal 40 are lower than the constant voltage point 23, an element 6 becomes conductive, and potential of the output terminal 50 is clamped to potential lower than the constant voltage point 23 by VBE of the element 6. Accordingly, when voltage drop of a constant voltage element 7 is set to VBE of the element 6, potential of the terminal 50 does not become lower than a constant voltage point 21, and operation of a constant current source transistor 2 becomes stable. When the element 6 is in the state of conduction, an emitter follower element 1 is in the state of cut off, and input resistance of a terminal 40 becomes very large value, and becomes far larger than input resistance at the time of conduction of the element 1.

Description

【発明の詳細な説明】 〔産業−にの利用分野〕 本発明は、エミッタフォロワ回路に係り、特に集積回路
上での使用に好適なエミッタフォロワ回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an emitter follower circuit, and particularly to an emitter follower circuit suitable for use on an integrated circuit.

〔従来の技術〕[Conventional technology]

第2図に周知のエミッタフォロワ回路を示す。 FIG. 2 shows a well-known emitter follower circuit.

第2図において、トランジスタ1のコレクタは直流電源
30に、ベースは入力端子40に、エミッタは出力端子
50にそれぞれ接続されている。また、トランジスタ2
のコレクタは出力端子に、ベースは抵抗13とダイオー
ド3の接続点(定電位点)21に、エミッタは抵抗]1
の一端にそれぞれ接続され、抵抗11の他端は接L(!
l電位に接続されている。さらに、抵抗1:3の一端は
直流電源;30に、抵抗13の他端はダイオード:3の
アノードに接続され、ダイオード3のカソードは抵抗1
2の一端に、抵抗12の他端は接地電位に接続されてい
る。ここで、トランジスタ2と抵抗11で定電流回路1
0を構成し、抵抗13とダイオード33と抵抗1−2で
定電圧回路20を構成している。
In FIG. 2, the collector of the transistor 1 is connected to a DC power supply 30, the base to an input terminal 40, and the emitter to an output terminal 50. Also, transistor 2
The collector is the output terminal, the base is the connection point (constant potential point) 21 between the resistor 13 and the diode 3, and the emitter is the resistor]1
are connected to one end of each, and the other end of the resistor 11 is connected to L(!
It is connected to l potential. Furthermore, one end of the resistor 1:3 is connected to the DC power supply; 30, the other end of the resistor 13 is connected to the anode of the diode: 3, and the cathode of the diode 3 is connected to the resistor 1.
2 and the other end of the resistor 12 is connected to ground potential. Here, a constant current circuit 1 is made up of a transistor 2 and a resistor 11.
A constant voltage circuit 20 is configured by a resistor 13, a diode 33, and a resistor 1-2.

第2図のエミッタフォロワ回路は、入力端子40に印加
される電圧信号をトランジスタ1のペースエミッタ電圧
分だけ降下させた電圧信シ)として出力端子50しこ伝
達するが、入力抵抗が高く、出力抵抗が低いことを特徴
としている。特に、入力抵抗に関しては、定電流負荷で
ある為に極めて高い値(概算、数百にΩ〜数MΩ)が期
待される。
The emitter follower circuit shown in FIG. 2 transmits the voltage signal applied to the input terminal 40 to the output terminal 50 as a voltage signal lowered by the pace emitter voltage of transistor 1, but the input resistance is high and the output It is characterized by low resistance. In particular, as for the input resistance, an extremely high value (approximately several hundred ohms to several Mohms) is expected since it is a constant current load.

ところで、一般的なPN接合分離方式を採用しているバ
イポーラ集積回路においては、NPNトランジスタのコ
レクタ電位がベース電位より低下し、その差が約0.5
〜0.7v程度となると、集積回路基板(P形半導体)
と該NPNトランジスタのベース、コレクタより構成さ
れる寄生PNPトランジスタが活性化され、基板電流を
生じ、時には、ラッチアップ、IC破壊に至る現象を誘
発することが知られている。従って、第2図のエミッタ
フォロワ回路を集積回路上で採用するに際しては、定電
流源トランジスタ2のコレクタ電位がベース電位より低
下しない様な対策が必要である。
By the way, in a bipolar integrated circuit that uses a general PN junction isolation method, the collector potential of the NPN transistor is lower than the base potential, and the difference is about 0.5.
~0.7v, integrated circuit board (P-type semiconductor)
It is known that a parasitic PNP transistor consisting of the base and collector of the NPN transistor is activated and generates a substrate current, sometimes inducing phenomena that lead to latch-up and IC destruction. Therefore, when employing the emitter follower circuit shown in FIG. 2 on an integrated circuit, it is necessary to take measures to prevent the collector potential of the constant current source transistor 2 from falling below the base potential.

従来、上記対索を施こしたエミッタフォロワ回路として
第3図に示す構成のものがある。第3図のエミッタフォ
ロワ回路が特徴とするところは。
Conventionally, there is a structure shown in FIG. 3 as an emitter follower circuit provided with the above pairing. What are the characteristics of the emitter follower circuit shown in Figure 3?

入力端子40に対し、定電圧回路24の定電圧点22を
ベース電位とするトランジスタ4、ダイオード5から成
るクランプ回路を付加した点にある。
A clamp circuit consisting of a transistor 4 and a diode 5 whose base potential is the constant voltage point 22 of the constant voltage circuit 24 is added to the input terminal 40.

該構成によれば、トランジスタ2のコレクタ電位がベー
ス電位より低下しない様に、入力電圧信号を制限するこ
とができる。なお、これの動作は特公昭60−4073
0号公報に詳述されている。
According to this configuration, the input voltage signal can be limited so that the collector potential of the transistor 2 does not fall below the base potential. In addition, the operation of this is based on the Special Publication Publication No. 60-4073.
It is detailed in Publication No. 0.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記第3図の構成においては、低電位の入力信号が印加
された際、トランジスタ4、ダイオード5が導通する為
、入力抵抗が低下しく約数Ω〜数十Ω)、前段回路に悪
影響を与えるという問題がある。
In the configuration shown in Figure 3 above, when a low-potential input signal is applied, transistor 4 and diode 5 become conductive, resulting in a decrease in input resistance (approximately several Ω to several tens of Ω), which adversely affects the preceding stage circuit. There is a problem.

本発明の目的は、高入力抵抗を維持し、かつ、定電流源
トランジスタの動作保護を可能とするエミッタフォロワ
回路を提供することにある〔問題点を解決するための手
段〕 上記目的は、エミッタフォロワ回路の出力端子に対して
、定電流源トランジスタのコレクタ電位を制限するクラ
ンプ回路を改番プることにより達成される。
An object of the present invention is to provide an emitter follower circuit that maintains a high input resistance and can protect the operation of a constant current source transistor. This is achieved by attaching a different number of clamp circuits that limit the collector potential of the constant current source transistor to the output terminal of the follower circuit.

〔作 用〕[For production]

クランプ回路は、定電流源トランジスタのベース電位を
基準とし、該トランジスタのコレクタ電位がある一定電
位より低下しない様に動作する。
The clamp circuit uses the base potential of the constant current source transistor as a reference and operates so that the collector potential of the transistor does not fall below a certain constant potential.

従って、該トランジスタの寄生PNPトランジスタは活
性化せず安定した動作を保障できる。また、入力端子に
はエミッタフォロワ・トランジスタのベースのみが接続
されており、高入力抵抗が期待できる。
Therefore, the parasitic PNP transistor of the transistor is not activated and stable operation can be ensured. In addition, only the base of the emitter follower transistor is connected to the input terminal, so high input resistance can be expected.

〔実施例〕〔Example〕

以下、本発明の一実施例について図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明のエミッタフォロワ回路の一実施例の構
成図であり、第2図及び第3図と同一部分については同
一番号を付し説明を省略する。第1図の特徴とするとこ
ろは、ダイオード3、抵抗12.16、定電圧素子7よ
り構成される定電圧回路25と、定電圧回路25の定電
圧点23にベースを接続し、直流電源30にコレクタを
接続し、出力端子50にエミッタを接続したトランジス
タ6を設けた点にある。
FIG. 1 is a configuration diagram of an embodiment of an emitter follower circuit according to the present invention, and the same parts as in FIGS. 2 and 3 are designated by the same reference numerals and the explanation thereof will be omitted. The features of FIG. 1 include a constant voltage circuit 25 composed of a diode 3, a resistor 12, 16, and a constant voltage element 7; a base is connected to the constant voltage point 23 of the constant voltage circuit 25; The transistor 6 is provided with a collector connected to the terminal 50 and an emitter connected to the output terminal 50.

第1図において、入力端子40に印加される入力電圧信
号が定電圧点23より低下すると、トランジスタ6が導
通状態となり、出力端子50の電位は、定電圧点23か
らトランジスタ6のベースエミッタ電圧だけ低下した電
位にクランプされる。
In FIG. 1, when the input voltage signal applied to the input terminal 40 drops below the constant voltage point 23, the transistor 6 becomes conductive, and the potential at the output terminal 50 decreases from the constant voltage point 23 by the base-emitter voltage of the transistor 6. Clamped to a reduced potential.

従って、例えば、定電圧素子7の電圧降下を1〜ランジ
スタロのペースエミッタ電圧と等しく設定すれば、出力
端子50の電位は、定電圧点21より低下することはな
く、定電流源トランジスタ2の安定動作が保証される。
Therefore, for example, if the voltage drop of the constant voltage element 7 is set equal to 1 to the pace emitter voltage of the transistor, the potential of the output terminal 50 will not drop below the constant voltage point 21, and the constant current source transistor 2 will stabilize. Operation is guaranteed.

また、入力電圧信号が低下し、トランジスタ6が導通し
た状態では、エミッタフォロワ・トランジスタ1は遮断
状態にあり、入力端子40の入力抵抗は極めて大きな値
(数MΩ以上)となり、トランジスタ1が導通状態にあ
る時の入力抵抗値より増加する。
Furthermore, when the input voltage signal decreases and the transistor 6 is conductive, the emitter follower transistor 1 is in a cutoff state, and the input resistance of the input terminal 40 becomes an extremely large value (several MΩ or more), so that the transistor 1 is in a conductive state. It increases from the input resistance value when it is at .

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明のエミッタフォロワ回路に
よれば、高入力抵抗を維持しつつ、定電流源トランジス
タの動作保護が可能となる。
As described above, according to the emitter follower circuit of the present invention, it is possible to protect the operation of the constant current source transistor while maintaining a high input resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のエミッタフォロワ回路の一実施例の構
成図、第2図は周知のエミッタフォロワ回路の構成図、
第3図は定電流源トランジスタの動作保護回路を付加し
た従来のエミッタフォロワ回路の構成図である。 1・・・エミッタフォロワ・トランジスタ。 2・・・定電流源トランジスタ、 3・・・ダイオード
、6・・・クランプ用トランジスタ、 7・・・定電圧素子、 11,12.16・・・抵抗、
」、0・・・定電流回路、 25・・・定電圧回路、2
1.23・・・定電圧点、 30・・・直流電源、40
・・・入力端子、 50・・・出力端子。 第   1  図 第  2   図 第  3  図 ′)2
FIG. 1 is a block diagram of an embodiment of the emitter follower circuit of the present invention, FIG. 2 is a block diagram of a well-known emitter follower circuit,
FIG. 3 is a configuration diagram of a conventional emitter follower circuit to which a constant current source transistor operation protection circuit is added. 1... Emitter follower transistor. 2... Constant current source transistor, 3... Diode, 6... Clamping transistor, 7... Constant voltage element, 11, 12.16... Resistor,
", 0...constant current circuit, 25...constant voltage circuit, 2
1.23... Constant voltage point, 30... DC power supply, 40
...Input terminal, 50...Output terminal. Figure 1 Figure 2 Figure 3 ')2

Claims (1)

【特許請求の範囲】[Claims] (1)コレクタを直流電源に、ペースを入出端子に、エ
ミッタを出力端子にそれぞれ接続した第1のトランジス
タと、第2のトランジスタのコレクタを電流出力端子と
し、上記第1のトランジスタと上記出力端子を共有する
定電流源回路とから成るエミッタフォロワ回路において
、上記第2のトランジスタのベース電位に対し一定の電
位点にベースを接続し、上記直流電源にコレクタを接続
し、エミッタを上記出力端子に接続した第3のトランジ
スタを設けたことを特徴とするエミッタフォロワ回路。
(1) A first transistor whose collector is connected to a DC power supply, a pace connected to an input/output terminal, and an emitter connected to an output terminal, and a second transistor whose collectors are connected to a current output terminal, and the first transistor and the output terminal In the emitter follower circuit, the base is connected to a constant potential point with respect to the base potential of the second transistor, the collector is connected to the DC power supply, and the emitter is connected to the output terminal. An emitter follower circuit comprising a third transistor connected to the emitter follower circuit.
JP20784886A 1986-09-05 1986-09-05 Emitsuta follower circuit Pending JPS6364407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20784886A JPS6364407A (en) 1986-09-05 1986-09-05 Emitsuta follower circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20784886A JPS6364407A (en) 1986-09-05 1986-09-05 Emitsuta follower circuit

Publications (1)

Publication Number Publication Date
JPS6364407A true JPS6364407A (en) 1988-03-22

Family

ID=16546527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20784886A Pending JPS6364407A (en) 1986-09-05 1986-09-05 Emitsuta follower circuit

Country Status (1)

Country Link
JP (1) JPS6364407A (en)

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