JPS6069902A - Signal output circuit - Google Patents

Abstract

PURPOSE:To make a reverse bias voltage applied to both transistors (TR) equal to a base-emitter voltage of the TRs by connecting a base-emitter circuit of the two TRs in anti-parallel between output points of two signals. CONSTITUTION:When a signal current source 2 is conducted, an ouptut is produced at a point A, a signal current source 3 is interrupted and no output is generated at a point B, then a TR4 acts like an emitter follower and a resistor 6 is its emitter resitance. Thus, a signal outputted to the point A from the signal current source 2 is outputted to a terminal 9 through emitter follower TRs 4, 7 by using a resistor 5 as an output load. A reverse bias voltage is applied between the base and emitter of the TR11 in this case and the TR11 is cut off, but the reverse bias voltage becomes equal to the base-emitter forward voltage VBE of the TR4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal output circuit capable of outputting two types of independent signals whose generation timings are opposite to each other from a single output terminal.

As a circuit for outputting two types of signals from a single output terminal, which have the conventional configuration and the timing at which the problem occurs, the signal output circuit with the circuit configuration shown in Fig. 1 is precisely limited. There is. In FIG. 1, 1 is a power supply voltage terminal, 2 and 3 are independent signal current sources, 4 is a transistor that connects the output points of the two signal current sources, 5 is an output load resistance of the signal current source 2,
6 is an output load resistance of the signal current source 3, 7 is an output emitter follower transistor, 8 is an emitter resistance of the emitter follower transistor 7, 9 is a signal output terminal, and 10 is a ground terminal. In the signal output circuit configured in this way, when the signal current source 2 is conductive and an output is generated, while the signal current source 3 is cut off, the transistor 4 simply functions as an output limiter follower, and the resistor 6 is connected to the transistor 4. serves as an emitter resistor. Note that the transistor 7 is an output emitter follower, and therefore, the signal output from the signal current source 2 is output to the terminal 9 through the emitter follower transistors 4 and 7 with the resistor 6 as an output load. On the other hand, when the signal current source 3 is conductive and an output is generated, and the signal current source 2 is cut off, almost no current flows through the resistor 5, and the base potential of the transistor 4 is approximately equal to the ground potential. Therefore, transistor 4 is in a cut-off state. Therefore, the signal outputted from the signal current source 3 is outputted to the terminal 9 through the emitter follower transistor 7 with the resistor 6 as an output load. In the conventional signal output circuit, one of the signals is output to the terminal 9 as described above, but when the latter circuit operates, that is,
During circuit operation in which the transistor 4 is cut off, the signal voltage generated by the signal current from the signal current source 3 flowing through the load resistor 6 is directly applied between the base and emitter of the transistor 4 as a reverse bias voltage.

By the way, if the transistor 4 is a planar transistor, its base-emitter-lid reverse withstand voltage is about 6 to 8V. Therefore, when a voltage higher than the pace-emitter reverse voltage of the transistor 4 is required as the signal voltage, the transistor 4 breaks down. In addition, if the reverse voltage (Iasumi pressure is 6V or less (signal voltage is 6V)
(below), even if transistor 4 does not break down, the current amplification factor of the transistor will deteriorate if the circuit operation in which the reverse voltage (Iasumi pressure) of about 5. This phenomenon is known to occur.

Note that when transistor 4 breaks down, a large current flows from the emitter to the base of transistor 4, so the emitter voltage of the transistor drops rapidly, and the signal output from signal current source 3 is directly transferred to the output terminal. An inconvenience arises that is not communicated to 9.

If the current amplification factor of the transistor 4 deteriorates, it will not affect the signal output from the signal current source 3;
The base current of the transistor 40 when the signal current source 2 is turned on increases compared to the base current before the current amplification factor deteriorates. For this reason, the current amplification factor of the current flowing through the resistor 6 decreases compared to before the deterioration, and the base voltage of the transistor 4 also decreases, resulting in the inconvenience that a desired signal output cannot be obtained.

Furthermore, in recent years, demands for higher integration and lower power consumption of semiconductor integrated circuits have led to the miniaturization of bipolar transistors.
Changes have also been brought about in the impurity concentration of each region forming a transistor, and the pace-emitter reverse breakdown voltage has decreased, and at present, transistors with this value of about 6V are increasing. When this type of transistor is used as the transistor 4, the current amplification factor deteriorates when the reverse bias voltage applied between the base and emitter is about 3V. In this way, in high-density integrated circuits, the upper limit of the reverse bias voltage between pace emitters becomes even lower. Therefore, when the illustrated signal output circuit is integrated, the above-mentioned problems become more noticeable, and there is a strong possibility that the intended circuit operation will not be carried out.

Purpose of the Invention The present invention is to obtain a stable output by eliminating the problem of applying a reverse bias voltage that exceeds the reverse breakdown voltage between pace emitters or the problem of deterioration of the current amplification factor of the l transistor, which existed in conventional signal output circuits. It is an object of the present invention to provide a signal output circuit that is capable of providing high-density integration and is also suitable for high-density integration.

Structure of the Invention The signal output circuit of the present invention includes bases of first and second transistors whose collectors are connected to a power supply terminal, respectively, between output points of first and second signals whose generation timings are opposite to each other. In addition to connecting the emitter circuits in antiparallel,
The first and second signals are extracted from either one of the output points of the first and second signals. According to this configuration, the reverse bias voltage applied to both transistors is 1[voltage (■B
E), which eliminates the application of a large reverse bias voltage.

DESCRIPTION OF EMBODIMENTS The present invention will now be described with reference to FIG. FIG. 2 is a diagram showing the configuration of the signal output circuit of the present invention. In the figure, 1 is a power supply voltage terminal, 2 and 3 are in reverse relationship with each other in signal generation timing, and are independent signal current sources, 4 is a transistor connecting the output points of two signal current sources, 5 is an output load resistance of signal current source 2, 6 is an output load resistance of signal current source 3, 7 is an output limiter follower transistor, and 8 is an emisota follower. The emitter resistance of the transistor 7, 9 a signal output terminal, and 10 a ground terminal are the same as these circuit elements. By the way, the circuit of the present invention is different from the conventional circuit in that a transistor 11 whose base emitter circuit is connected in antiparallel to the base emitter circuit of the transistor 4 is added.

In the signal output circuit of the present invention configured in this way,
When the signal current source 2 is conductive and an output is generated at point A, while the signal current source 3 is cut off and no output is generated at point B, the transistor 4 acts as an emitter follower, and the resistors act as emitter resistances. becomes. Therefore, the signal output from the signal current source 2 to point A is transmitted through the emitter follower transistors 4 and 7 to the terminal 9 with the resistor 6 as the output load.
is output to. At this time, a reverse bias voltage is applied between the base and emitter of the transistor 11, and the transistor 11
is in a cant-off state, but its reverse bias voltage is equal to the base-emitter forward voltage vBE of the transistor 4, which is less than 1V. On the other hand, signal current source 3
When conducts and an output occurs at point B, the output signal is
Resistor 6 is the output load, emitter follower transistor 7
It is output to terminal 9 through. At this time, the transistor 11 must operate in the same way as an emitter follower, and the resistor 5
plays the role of the emitter resistance of the transistor 11. Therefore, even if the signal current source 2 is cut off and no output is generated at point A, current flows through the resistor 5. Under this situation, a reverse bias voltage is applied between the base and emitter of transistor 4, and transistor 4 is in a cutoff state, but this reverse bias voltage is equal to the base-emitter forward voltage BE of transistor 11, which is also It is less than 1 cm in size. That is, in the signal output circuit of the present invention, the magnitude of the reverse bias voltage applied between the base and emitter of the transistor that connects the output points of two signals is fixed to a magnitude equal to the pace-emitter forward voltage vBE of the transistor. be done.

Note that in the illustrated circuit, the base of the emisotahoroff transistor 70 is connected to point B, which is the output point of the signal current source 3, but it may be configured to be connected to point A, which is the output point of the signal current source 2. .

Effects of the Invention In the signal output circuit of the present invention, the reverse bias voltage applied between the base and emitter of the transistor can be fixed to a small value of 1 V or less, and therefore, the disadvantage of causing breakdown of the transistor can be prevented. Of course, the inconvenience of deterioration of the current amplification factor can also be prevented. Therefore, even a signal voltage larger than the pace-emitter reverse breakdown voltage of the transistor can be stably output. Furthermore, the signal output circuit of the present invention is suitable for high-density integrated circuits in which the pace-emitter reverse breakdown voltage of transistors is low. Furthermore, in the signal output circuit of the present invention, the output may be taken out from either side of the signal current sources 2 and 3;
This also has the effect of increasing the degree of freedom in circuit design.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional signal output circuit, and FIG. 2 is a diagram showing an embodiment of the signal output circuit of the present invention. 1...Power supply voltage terminal, 2,3...Signal current source, 4.11...Signal output point, connection transistor, 6.6...Output load resistance , 7...Output limiter follower transistor, 8...Emitter resistor, 9...Output terminal, 1o...Ground terminal.

Claims (1)

[Claims] Pace emitter circuits of first and second transistors whose collectors are respectively connected to the power supply terminal are connected in antiparallel between the output points of the first and second signals whose generation timings are opposite to each other; A signal output circuit characterized in that the first and second signals are extracted from either one of the output points of the first and second signals.