JPS6366096U - - Google Patents

Info

Publication number
JPS6366096U
JPS6366096U JP15739286U JP15739286U JPS6366096U JP S6366096 U JPS6366096 U JP S6366096U JP 15739286 U JP15739286 U JP 15739286U JP 15739286 U JP15739286 U JP 15739286U JP S6366096 U JPS6366096 U JP S6366096U
Authority
JP
Japan
Prior art keywords
board
control signal
inverter device
terminals
modular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15739286U
Other languages
Japanese (ja)
Other versions
JPH069592Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15739286U priority Critical patent/JPH069592Y2/en
Publication of JPS6366096U publication Critical patent/JPS6366096U/ja
Application granted granted Critical
Publication of JPH069592Y2 publication Critical patent/JPH069592Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案による基板と、複数個並べられ
たモジユール素子との取り付け状態を示す図、第
2図は第1図の断面図、第3図は第2図の要部部
分図、第4図は従来例の第2図相当図、第5図は
別の従来例の素子取付け構造図、第6図は4IN
1タイプのMOS―FETを3個使用して並列接
続とした時の回路図を示す。 1……放熱板、2……モジユール化した素子、
3……ネジ、4……フアストン端子、5……入出
力配線、6……制御信号配線、7……制御信号配
線を採用した基板、8……コネクタ、9……スペ
ーサー、10……制御回路基板。
Fig. 1 is a diagram showing how the substrate according to the present invention is attached to a plurality of module elements lined up, Fig. 2 is a cross-sectional view of Fig. 1, and Fig. 3 is a partial view of the main part of Fig. 2; Figure 4 is a diagram corresponding to Figure 2 of the conventional example, Figure 5 is a diagram of the element mounting structure of another conventional example, and Figure 6 is a diagram of 4IN.
A circuit diagram when three MOS-FETs of one type are used and connected in parallel is shown. 1... Heat sink, 2... Modular element,
3... Screw, 4... Faston terminal, 5... Input/output wiring, 6... Control signal wiring, 7... Board adopting control signal wiring, 8... Connector, 9... Spacer, 10... Control circuit board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力端子と出力端子と制御信号端子を有するモ
ジユール化した素子を複数個並列接続して用いて
直流を交流に交換するインバータ装置において、
前記モジユール化した素子の上に前記入力端子と
前記出力端子とを挿通する貫通孔と前記モジユー
ル化した素子の取付けネジに対応する部分に設け
た貫通孔とを有し制御信号用の回路を印刷した基
板を取付け、この基板上の回路で各素子への制御
信号を並列することを特徴とするインバータ装置
。
In an inverter device that exchanges direct current to alternating current using multiple modular elements having input terminals, output terminals, and control signal terminals connected in parallel,
The modular element has a through hole through which the input terminal and the output terminal are inserted, and a through hole provided in a portion corresponding to the mounting screw of the modular element, and a control signal circuit is printed thereon. An inverter device is characterized in that a circuit board is mounted on the board, and control signals to each element are paralleled by circuits on the board.
JP15739286U 1986-10-16 1986-10-16 Inverter device Expired - Lifetime JPH069592Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15739286U JPH069592Y2 (en) 1986-10-16 1986-10-16 Inverter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15739286U JPH069592Y2 (en) 1986-10-16 1986-10-16 Inverter device

Publications (2)

Publication Number Publication Date
JPS6366096U true JPS6366096U (en) 1988-05-02
JPH069592Y2 JPH069592Y2 (en) 1994-03-09

Family

ID=31079896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15739286U Expired - Lifetime JPH069592Y2 (en) 1986-10-16 1986-10-16 Inverter device

Country Status (1)

Country Link
JP (1) JPH069592Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024241362A1 (en) * 2023-05-19 2024-11-28 三菱電機モビリティ株式会社 Electric power conversion device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024241362A1 (en) * 2023-05-19 2024-11-28 三菱電機モビリティ株式会社 Electric power conversion device

Also Published As

Publication number Publication date
JPH069592Y2 (en) 1994-03-09

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