JPS6366100B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a memory switch system for counting the amount of information, and more particularly to a switching system that allows charging for the amount of information by counting the amount of information with a memory switch of a line exchange. It is something.

[Prior art]

Memory switch type data exchangers have conventionally used memory switches to convert time slots, and do not monitor the amount of information passing through them.

FIG. 1 is a block diagram of a time slot conversion section of a conventional memory switch, and FIG. 2 is a diagram showing an operation cycle of the time slot conversion holding memory in FIG.

In Figure 1, 10 is the entrance highway, 11
data buffer memory for temporarily accumulating data of the entering highway corresponding to each time slot; 12;
13 is a counter for generating address information for accessing the time slot conversion holding memory 12; An address control line 15 is used to access the time slot conversion holding memory 12 based on address information, an address control line 15 is used to specify a write address to the buffer memory 11, and 16 corresponds to each address of the time slot conversion holding memory 12. A parity generator adds a parity bit to the information; 17 is a parity checker that checks the parity bit of the retained memory information; and 18 is an output highway. In the operation cycle of the time slot conversion holding memory 12,
The A cycle is a soft cycle, and is a cycle for writing to or reading from the holding memory 12 when an order for channel control is sent by the call processing program, and the B cycle is for reading the read address of the data buffer memory 11. The C cycle is a hard cycle for reading from the address of the time slot conversion holding memory 12 based on the address information generated by the address counter 13. The C cycle is a hard cycle for writing to the holding memory 12 in order to add a parity bit to the holding memory 12. It is. In the conventional memory switch system, the above-mentioned block is the basic configuration, and after writing the communication path control path information into the holding memory 12, the call processing program only monitors the disconnection information. However, no means had been taken to monitor the information carried by the transmission path data passing through the communication path.

〔the purpose〕

An object of the present invention is to improve such conventional drawbacks and provide a memory switch system for counting the amount of information that can count the amount of information for each subscriber on a transmission path and use it as billing information. be.

[Summary of the invention]

The memory switch method for counting the amount of information of the present invention is as follows:
In order to convert the data of the time slot on the incoming highway to the time slot on the outgoing highway,
In a memory switch equipped with a buffer memory for data storage and a holding memory for storing the access address of the buffer memory, it is determined whether the information carried in a given time slot is the same as the information stored in the buffer memory one data frame before the information. a memory for accumulating the cases where the comparison results are not the same for each time slot and storing the accumulation results;
It is characterized in that it is equipped with a buffer memory for time slot conversion on two sides, and counts the amount of information carried by each time slot by switching write control and read control between the two buffer memories for each data frame. be.

[Embodiments of the invention]

FIG. 3 is a block diagram of a memory switch showing the first embodiment of the present invention, and FIG. 4 is a diagram showing an operation cycle of the data buffer memory of FIG. 3.

In FIG. 3, 301A and 301B are data buffer memories prepared on two sides on the inbound highway for storing parallel data signals of, for example, 8 bits and converting time slots. 302A and 302B are selectors; 303 is an address holding memory that holds read addresses from the data buffer memories 301A and 301B for time slot conversion;
04 is a counter that operates in synchronization with the clock phase of the outbound highway, 305 is a counter that operates in synchronization with the transmission clock of the inbound highway, and 306
308 is a comparison circuit; 307 is an addition circuit for adding +1 to the information amount counting result based on the comparison result; 309
A and B are selectors for selecting read/write control signals for the data buffer memories 301A and 301B, and 310A and 310B are read/write control signals.

As shown in FIG. 4, the operation cycle pattern of the two buffer memories A and B changes every data frame.

A case will be described in which the data buffer 301A operates in the upper operation cycle of FIG. 4 and the data buffer memory 301B operates in the lower operation cycle of FIG. 4 when receiving the #N data frame.

In FIG. 4, t is the data frame switching time, T is the time corresponding to one time slot time on the transmission path, R ₁ is a read cycle for reading data and comparing information in the #N data frame, R ₂
is a read cycle for reading data and comparing information in the #(N-1) data frame, _R3 is a read cycle for reading and exchanging data in the #(N-1) data frame, and W is a write cycle. ,
#N Indicates writing of data in the data frame. The data signal on the incoming highway 10 is written to the same address of 301A immediately after the data information from the address of 301A is read by the address indicated by the time slot counter 305 within the time of one time slot on the highway. be included. Note that the data signal in the above read #(N-2) data frame from 301A is as follows:
#(N) stored at the same address in 301B
-1) The comparison circuit 308 compares and verifies the read information of the data signal in the data frame. At this time, as a result of the comparison, the information carried in the time slot in the #(N-1) data frame is #(N
-2) If the information does not match the information carried by the time slot in the data frame, the +1 addition circuit 307 is operated and the information amount counting memory 30 is
6 for each time slot accumulated (per subscriber)
Add +1 to the information count accumulated in . If the above comparison results match, #(N-1)
It is determined that the information carried by the time slot in the data frame is not significant, and no +1 addition is performed, causing the information count to remain the same as when #(N-2) data frames were received. In this way, the counter 30 is synchronized with the transmission line clock phase.
According to the address information outputted by 5, the data signals are simultaneously read from the data buffer memories 301A and 301B, and the information is compared.
It is determined whether the signal at the time slot one data frame ago and the signal at the same time slot two data frames ago are the same, and only when a different data signal is carried, the time slot in the information counting memory is updated. By adding +1 to the contents of the address corresponding to the lot, it is possible to count the amount of information in units of octets (8 bits).

In FIG. 5, a shows the case when the switching signal 〓〓 is input to the selector 302A, b shows the case when the switching signal 〓〓 is input to the selector 302B, and c shows the case when the read/write control signal is input to the data buffer 301B. d is the case where a read/write control signal is input to the data buffer 301A. Also, 1 and 3 are holding memory 3
03 output is selected, 2 and 4 are selector 302A,
B indicates the operation of selecting the output of the counter 305, respectively.

In FIG. 5, in the exchange operation when #N data frame is received, data is read based on the address information output from the holding memory 303 by the control signal of the data buffer memory read cycle (〓〓, 〓〓) of the data buffer memory 301B. buffer memory 301
The data signal corresponding to the address in B is read out onto the outgoing highway 18). In exactly the same way, when receiving a data frame numbered (N+1), the data signal received within the #Nth data frame stored in the data buffer memory 301A and the #(N)th data frame stored in the data buffer memory 301B are combined. -1) is compared with the data signal received within the data frame, and the exchange operation is performed in the data buffer memory 30.
This can be achieved with a read cycle of 1A.
In this embodiment, a case is shown in which information is compared by going back by two data frames, but this idea can be easily applied to a method of going back and comparing M data frames. In this case, only the M side of the buffer is prepared, and when the information carried by the time slot in consecutive M data frames is the same, the contents of the information amount counting memory corresponding to the time slot are added by +1. It is sufficient if the configuration is such that Furthermore, the number of parallel bits of incoming highway data can easily be expanded or reduced to P bits.

Although the present embodiment shown in FIG. 3 shows an example in which the address holding memory 303 and the information amount counting holding memory 306 are configured as physically separate blocks, these two memory blocks are arranged as shown in FIG. As shown in the embodiment, it is possible to have an integrated configuration. Reference numeral 601 denotes the above-mentioned integrated memory block, which has the function of an address control holding memory for performing exchange and the function of a holding memory for information amount counting. 602 is a selector for switching between the time slot counter 304 which operates in synchronization with the incoming highway clock and the counter 305 which operates in synchronization with the outgoing highway clock.

Further, DFSW is a data frame switching signal. Conventionally, circuit switching equipment did not have any means for counting the amount of information, but this
This problem can be overcome by referring to FIG. Also,
By comparing and collating the data signals passing through the communication path over several frames, meaningful information can be monitored, but invalid information can be generated due to terminal failures, transmission path failures, etc. Even when the information is transmitted, the exchange side can take this state into account and count the correct amount of information. Furthermore, in this embodiment, an example of a communication path control configuration has been described in which the data signal of two data frames before is compared with the data signal of one data frame before, but this method can easily be applied to the data signal of one data frame before. It can also be applied to the case where the signal in the current data frame is compared with the signal in the current data frame.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to compare and match data signals passing through a communication path over several frames, and when there is a mismatch, it is possible to detect the passage of meaningful data. The amount can be counted and used as billing information.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a time slot conversion section of a conventional memory switch, FIG. 2 is a diagram showing an operation cycle of the time slot conversion holding memory in FIG. 1, and FIG. 3 is a diagram showing a first embodiment of the present invention. An example block diagram of a memory switch, FIG.
5 is a diagram showing the switching signal of the selector in FIG. 3, and FIG. 6 is a block diagram of a memory switch showing a second embodiment of the present invention. It is. 10... Entry highway, 11... Data buffer memory, 12... Holding memory, 13... Counter, 14... Address control line (write control),
15...Address control line (read control), 16...
... Parity generator, 17... Parity checker, 18... Exit highway, 301A, B...
Data buffer memory, 302A, B... Selector, 303... Address holding memory, 304...
Counter (synchronized with the clock phase of the incoming highway), 305...Counter (synchronized with the clock phase of the outgoing highway), 306...memory for counting the amount of information, 307...+1 addition circuit, 308...comparison circuit, 309... Selector, 310...read/write control signal, 601...integrated memory block,
602...Selector.

Claims (1)

[Claims] 1. In order to convert data in a time slot on an incoming highway to a time slot on an outgoing highway, a memory switch is provided with a buffer memory for data storage and a holding memory for storing an access address of the buffer memory, A two-sided buffer memory for time slot conversion, means for comparing the information carried in any time slot with the information stored in the buffer memory one data frame before that information, and a means for comparing the result of the above comparison for each time slot. A means is provided for accumulating the number of mismatches and storing the accumulated value, and the amount of information carried in the time slot is counted by switching write control and read control between the two buffer memories for each data frame. A memory switch method for counting the amount of information. 2. The memory switch system for counting the amount of information according to claim 1, wherein the storage means for the integrated value shares the same memory with a holding memory for storing access addresses.