JPS6366451B2 - - Google Patents
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- Publication number
- JPS6366451B2 JPS6366451B2 JP16176782A JP16176782A JPS6366451B2 JP S6366451 B2 JPS6366451 B2 JP S6366451B2 JP 16176782 A JP16176782 A JP 16176782A JP 16176782 A JP16176782 A JP 16176782A JP S6366451 B2 JPS6366451 B2 JP S6366451B2
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- Japan
- Prior art keywords
- frequency
- loss
- equalized
- capacitor
- equalization
- Prior art date
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G5/00—Tone control or bandwidth control in amplifiers
- H03G5/02—Manually-operated control
Landscapes
- Filters That Use Time-Delay Elements (AREA)
- Amplifiers (AREA)
Description
この発明はスイツチトキヤパシタフイルタを用
いて線路損失を補償すると共に波形整形を行なう
等化増幅回路に関するものである。
<従来技術>
信号伝送における線路損失は一般に第1図に示
すように周波数fの平方根にほゞ比例し、かつ線
路の長さが長くなるほど同一周波数の損失が大き
くなる。第1図ではパラメータは線路の長さを示
し、l1>l2>l3である。このような線路損失をス
イツチトキヤパシタフイルタ(以下SCFと呼ぶ)
を用いて等化するためには一般に第2図に示すよ
うな構成がとられていた。線路損失補償用SCF1
00に波形整形用SCF200が信号入力端子1及
び等化波形出力端子2間に縦続接続される。線路
損失補償用SCF100において入力端子1は容量
素子6を通じて演算増幅器A1の反転入力側に接
続されると共にアナログスイツチS1,S2により容
量素子5が入力端子1及び演算増幅器A1の反転
入力側に接続され、この容量素子5の両端はスイ
ツチS1,S2により接地側に切替え接続することが
できる。演算増幅器A1の反転入力側及び出力側
間に容量素子4が接続されると共に、これらの間
にアナログスイツチS3,S4で容量素子7が接続さ
れ、またスイツチS3,S4を切替えて容量素子7の
両端を接地することができるようにされている。
演算増幅器A1の非反転入力側は接地され、出力
側は出力端子3に接続される。波形整形用SCF2
00において、線路損失補償用SCF100の出力
端子3が容量素子10を通じて演算増幅器A2の
反転入力側に接続され、容量素子9の一端はアナ
ログスイツチS5により端子3と演算増幅器A2の
反転入力側とに切替え接続され、他端は接地され
る。演算増幅器A2の反転入力側及び出力側間に
容量素子8が接続され、またこれら間に容量素子
11の両端がアナログスイツチS6,S7により接続
されたり、接地される。演算増幅器A2の非反転
入力側は接地され、出力側は出力端子2に接続さ
れる。
なお第2図は1次のSCFで実現した例である
が、2次以上の高次のSCFで実現することも可能
である。
第2図の端子1から入力したサンプルホールド
された波形は、サンプリングクロツクと同期して
アナログスイツチS1〜S4がφ側、側に交互に切
り換えられて、線路損失補償用SCF100で積分
され、端子3に出力される。端子1の入力電圧を
Vi、端子3の出力電圧をV3、容量素子4〜7の
容量値をC4〜C7、サンプリングクロツク周波数
をfsとすると、線路損失補償用SCF100の伝達
関数は次式のようになる。
V3/Vi=−(C5/C4+C6/C4)−C6/C4Z-1/(1+C
7/C4)−Z-1
Z=exp(j2πf/fs) (1)
容量値C5〜C7を変化させることにより任意の
極、零点、最大利得を得ることができる。容量値
C5〜C7が各種の容量5〜7をそれぞれ用意し、
スイツチでこれら容量素子を切り換えて使用する
ことにより第1図に示すような各種の線路損失を
等化することが可能となる。
また波形整形用SCF200は低域通過フイルタ
として構成され、端子3の電圧はサンプリングク
ロツクと同期してスイツチS5〜S7がφ側、側に
交互に切り換えられて波形整形用SCF100で積
分され、端子2に出力される。端子3の電圧V3
と端子2の出力V0の間の伝達関数は容量素子8
〜11の容量値をC8〜C11とし、サンプリングク
ロツクの周波数をfsとすると次式で表わされる。
V0/V3=−C10/C8+(C9/C8−C10/C8)Z-1/(
1+C11/C8)−Z-1
Z=exp(j2πf/fs) (2)
容量値C9〜C11を選択することにより、低域通
過フイルタのしや断周波数を変えることができる
ため、伝送速度にあわせたしや断周波数を選ぶこ
とができる。
m種類の伝送速度に対して、最大Gデシベルの
線路損失を等化するため、従来は第2図中の容量
素子5〜7に対しては第3図に示すような形で、
また第2図の容量素子9〜11に対しては第4図
に示すような形で実現し、それぞれの線路損失特
性を等化していた。最大損失Gデシベルを△Gデ
シベルステツプで等化することを考えると、各伝
送速度に対して等化すべき周波数特性の数nは次
式で示される。
n=G/△G (3)
第3図において、1番目の伝送速度に対してn
通りの線路等化特性を得るため、あらかじめC11
〜C1oのn個の容量素子からなる容量素子群を用
意し、それらの容量素子をその両端に対となつて
設けられたアナログスイツチS11〜S1oで切り換え
て実現する。またm種類の伝送速度に対して適用
するためには前記容量素子群をm組用意すればよ
い。このとき端子21,22の間の容量CTは
CT=n
〓q1 o
〓r=1
kqrCqr (4)
たゞし、kqrは対となつたアナログスイツチSqr
が導通状態のとき1、非導通状態のとき0であ
る。
波形整形用SCF200については伝送速度ごと
に低域通過フイルタのしや断周波数を変えればよ
い。そのため第4図においてm個の容量素子C1
〜Cnをあらかじめ用意しておき、伝送速度に応
じて容量素子の両端に対となつて設けられたアナ
ログスイツチSW1〜SWnで切り換え、しや断周
波数をかえることにより実現する。第3図、第4
図に示した方法を用いた場合の線路損失補償SCF
100、波形整形フイルタ200及び第2図の入
力端子1から等化波形出力端子2までの総合の周
波数特性を第5図に示す。第5図は2種類の伝送
速度に対して適用できるようにした場合の周波数
特性であり、1番目の伝送速度の特性を実線で、
2番目の伝送速度の特性を点線で示し、Aは線路
損失補償用SCF100、Bは波形整形用SCF20
0、Cは総合の各周波数特性である。
第3図、第4図に示した方法でm種類の伝送速
度に対してそれぞれn通りの線路長の損失を等化
するための全容量素子の個数NTは
NT=α・m・n+βm (4)
たゞし、αは線路損失補償用SCF100の積分
容量素子以外の容量素子の数、βは波形整形用
SCF200の積分容量素子以外の容量素子の数で
ある。(4)式より明らかなように第3図、第4図に
よる従来回路では適用する伝送速度の数mが増え
るとそれに比例して容量素子の数を増やさなけれ
ばならないため、これをLSI化する場合にはチツ
プ占有面積が増大する欠点があつた。また第3
図、第4図に示したように容量素子の数と同数組
のアナログスイツチが付加されているため、その
浮遊容量が大きくなり特性が劣化し、高精度な等
化が困難となる欠点があつた。
<発明の目的>
この発明はこれら欠点を除去し、LSI化を図つ
た場合、高精度かつチツプ占有面積の小さな等化
増幅回路を提供するものである。
<実施例>
第6図はこの発明の実施例を示し、第2図の場
合と同様に線路損失補償用SCF100と波形整形
用SCF200とが信号入力端子1と等化波形出力
端子2との間に縦続接続される。容量素子5とし
て容量素子C51〜C5oがアナログスイツチで選択的
に接続され、同様に容量素子6,7,9,10,
11はそれぞれ容量素子がアナログスイツチで選
択的に接続される。
線路補償用SCF100、波形整形用SCF200
の伝達関数は容量素子群5〜7,9〜11の容量
値をCi(i=5〜7、9〜11)とすると、それぞ
れ前出の式(1)、式(2)であらわされる。またこのと
きCiは次式で表わされる。
Ci=
〓q
kiqCiq(i=5〜7、9〜11) (5)
この実施例では線路損失補償用SCF100を構
成する容量素子群5〜7の容量値Ciq(i=5〜
7、q=1〜n、k、l、…)を以下に示すよう
に決める。以下の説明ではm種類の伝送速度に対
して、すべて等化すべき最大損失をGデシベル、
等化ステツプを△Gデシベルとするが、同様にし
て等化すべき最大損失、等化ステツプが伝送速度
ごとに変わる場合にも適用できる。また最も高周
波域まで等化すべき伝送速度のものを第1の伝送
速度と呼び、第m番目に高周波域まで等化すべき
伝送速度のものを第mの伝送速度と呼ぶ。
(1) まず第1の伝送速度に対して△Gステツプで
等化するためn個(n=G/△G)の容量素子を
用意する。
(2) 次に第1の伝送速度の周波数特性で第2伝送
速度の周波数特性を等化できない分について容
量素子5〜7に対する容量素子を用意する。第
2の伝送速度で等化すべき最大周波数が、第1
の伝送速度で等化すべき最大周波数の1/P2
であるとすると、一般に線路損失は周波数の平
方根にほゞ比例するため第1の伝送速度を等化
する周波数特性で第2の伝送速度の最大線路損
失Gの1/√2までを等化できる。そのため
第2の伝送速度で未等化の損失範囲G/√2
〜Gまでを等化するための容量素子を用意す
る。新たに用意すべき容量素子の数をN2とす
ると次式で表わされる。
(3) 以下第3〜第mの伝送速度についても同様に
第(q−1)番目(q=3〜m)までの周波数
特性で未等化の部分を△Gデシベル以下のステ
ツプで等化できるように容量素子を用意する。
波形整形用SCF200については伝送速度ごと
に低域通過フイルタのしや断周波数を変えればよ
いため、第6図に示したように容量素子群9〜1
1にあらかじめm個ずつの容量素子Cir(i=9〜
11、r=1〜m)を用意しておき、容量素子Cir
の両端に対となつて設けられたアナログスイツチ
Sir(i=9〜11、r=1〜m)で切り換えてm種
類のしや断周波数を得る。
この実施例を用いた場合の線路損失補償用SCF
(第6図100)、波形整形用SCF(第6図200)
及び第6図の入力端子1から等化波形出力端子2
までの総合の周波数特性をそれぞれ第7図に示
す。第7図は2種類の伝送速度に対して適用でき
るようにした場合の例であり、Aは線路損失補償
用SCF、Bは波形整形用SCF、Cは総合の周波数
特性である。
第q番目の伝送速度で等化すべき最大周波数が
第1の伝送速度で等化すべき最大周波数の1/
Prであるとし、線路損失補償用SCF100及び
波形整形用SCF200の積分容量素子以外の容量
素子の数をそれぞれα,βとすると、m種類の伝
送速度に対して、△Gデシベル以下のステツプで
線路損失を等化するための積分容量素子以外の全
容量素子の個数NTは次式で表わされる。
<効果>
この実施例では線路損失補償用SCF100に必
要とする容量素子の数が適用対象となる伝送速度
の数mに比例して増加させる必要がないため、従
来よりも少ない容量素子の数、少ないアナログス
イツチの数で複数の伝送速度の等化増幅器として
機能させることができる。
一例として2種類及び3種類の伝送速度に適用
可能とした場合の容量素子及びアナログスイツチ
の必要とする組数を表1に示す。
The present invention relates to an equalization amplifier circuit that uses a switched capacitor filter to compensate for line loss and to perform waveform shaping. <Prior Art> Line loss in signal transmission is generally proportional to the square root of the frequency f, as shown in FIG. 1, and the longer the length of the line, the greater the loss at the same frequency. In FIG. 1, the parameters indicate the length of the line, l 1 >l 2 >l 3 . This kind of line loss is processed by a switch capacitor filter (hereinafter referred to as SCF).
In order to perform equalization using , a configuration as shown in FIG. 2 was generally adopted. SCF1 for line loss compensation
00, a waveform shaping SCF 200 is connected in cascade between a signal input terminal 1 and an equalized waveform output terminal 2. In the SCF 100 for line loss compensation, input terminal 1 is connected to the inverting input side of operational amplifier A 1 through capacitive element 6, and capacitive element 5 is connected to input terminal 1 and the inverting input of operational amplifier A 1 by analog switches S 1 and S 2 . Both ends of the capacitive element 5 can be switched and connected to the ground side by switches S 1 and S 2 . A capacitive element 4 is connected between the inverting input side and the output side of the operational amplifier A1 , and a capacitive element 7 is connected between them by analog switches S3 and S4 , and the switches S3 and S4 are switched. Thus, both ends of the capacitive element 7 can be grounded.
The non-inverting input side of the operational amplifier A1 is grounded, and the output side is connected to the output terminal 3. SCF2 for waveform shaping
00, the output terminal 3 of the SCF 100 for line loss compensation is connected to the inverting input side of the operational amplifier A2 through the capacitive element 10, and one end of the capacitive element 9 is connected to the terminal 3 and the inverting input side of the operational amplifier A2 by the analog switch S5. The other end is grounded. A capacitive element 8 is connected between the inverting input side and the output side of the operational amplifier A2 , and both ends of the capacitive element 11 are connected between these by analog switches S6 and S7 or grounded. The non-inverting input side of the operational amplifier A2 is grounded, and the output side is connected to the output terminal 2. Although FIG. 2 shows an example realized with a first-order SCF, it is also possible to realize it with a second-order or higher-order SCF. The sampled and held waveform input from terminal 1 in Fig. 2 is integrated by the line loss compensation SCF 100 by switching the analog switches S 1 to S 4 alternately to the φ side and to the φ side in synchronization with the sampling clock. , is output to terminal 3. Input voltage of terminal 1
V i , the output voltage of terminal 3 is V 3 , the capacitance values of capacitive elements 4 to 7 are C 4 to C 7 , and the sampling clock frequency is f s , the transfer function of the SCF 100 for line loss compensation is as follows: become. V 3 /V i =-(C 5 /C 4 +C 6 /C 4 )-C 6 /C 4 Z -1 /(1+C
7 /C 4 )−Z −1 Z=exp(j2πf/f s ) (1) Any pole, zero point, or maximum gain can be obtained by changing the capacitance values C 5 to C 7 . Capacity value
C 5 to C 7 prepare various capacities 5 to 7, respectively.
By switching and using these capacitive elements with a switch, it becomes possible to equalize various line losses as shown in FIG. The waveform shaping SCF 200 is configured as a low-pass filter, and the voltage at terminal 3 is integrated by the waveform shaping SCF 100 by switching switches S 5 to S 7 alternately to the φ side and φ side in synchronization with the sampling clock. , is output to terminal 2. Voltage at terminal 3 V 3
The transfer function between the output V 0 of terminal 2 and the capacitive element 8
.about.11 are C8 to C11 , and the frequency of the sampling clock is fs , it is expressed by the following equation. V 0 /V 3 = −C 10 /C 8 + (C 9 /C 8 −C 10 /C 8 )Z -1 /(
1+C 11 /C 8 )−Z -1 Z=exp(j2πf/f s ) (2) By selecting the capacitance values C 9 to C 11 , the cutoff frequency of the low-pass filter can be changed. , you can select the cutting frequency according to the transmission speed. In order to equalize the maximum G decibel line loss for m types of transmission speeds, conventionally the capacitive elements 5 to 7 in Fig. 2 are connected in the form shown in Fig. 3.
Further, the capacitive elements 9 to 11 in FIG. 2 were realized in the form shown in FIG. 4, and the line loss characteristics of each were equalized. Considering that the maximum loss G decibel is equalized in ΔG decibel steps, the number n of frequency characteristics to be equalized for each transmission rate is expressed by the following equation. n=G/△G (3) In Figure 3, n for the first transmission speed
In order to obtain the normal line equalization characteristics, C 11
This is realized by preparing a capacitive element group consisting of n capacitive elements of ~ C1o , and switching these capacitive elements with analog switches S11 ~ S1o provided in pairs at both ends thereof. Further, in order to apply the present invention to m types of transmission speeds, it is sufficient to prepare m sets of the capacitive element groups. At this time, the capacitance C T between terminals 21 and 22 is C T = n 〓 q1 o 〓 r=1 k qr C qr (4) where k qr is the paired analog switch S qr
It is 1 when it is in a conductive state, and it is 0 when it is in a non-conductive state. Regarding the waveform shaping SCF 200, the cutting frequency of the low-pass filter may be changed for each transmission speed. Therefore, in Fig. 4, m capacitive elements C 1
This is achieved by preparing C n in advance and changing the shearing frequency by switching it with analog switches SW 1 to SW n provided in pairs at both ends of the capacitive element according to the transmission speed. Figures 3 and 4
Line loss compensation SCF when using the method shown in the figure
100, the waveform shaping filter 200, and the overall frequency characteristics from the input terminal 1 to the equalized waveform output terminal 2 in FIG. 2 are shown in FIG. Figure 5 shows the frequency characteristics when it is applicable to two types of transmission speeds, and the characteristics of the first transmission speed are shown as solid lines.
The characteristics of the second transmission speed are shown by dotted lines, where A is SCF100 for line loss compensation and B is SCF20 for waveform shaping.
0 and C are overall frequency characteristics. The total number of capacitive elements N T to equalize the losses of n different line lengths for m different transmission speeds using the method shown in Figures 3 and 4 is N T = α・m・n+βm (4) Where, α is the number of capacitive elements other than the integral capacitive element of SCF100 for line loss compensation, and β is for waveform shaping.
This is the number of capacitive elements other than the integral capacitive element of the SCF 200. As is clear from Equation (4), in the conventional circuits shown in Figures 3 and 4, as the number of meters of applied transmission speed increases, the number of capacitive elements must be increased in proportion to the number of meters, so it is necessary to convert this into an LSI. In some cases, there was a disadvantage that the area occupied by the chip increased. Also the third
As shown in Figure 4, since the same number of analog switches as the number of capacitive elements are added, the stray capacitance increases, deteriorating the characteristics, and making highly accurate equalization difficult. Ta. <Objective of the Invention> The present invention eliminates these drawbacks and provides an equalization amplifier circuit which is highly accurate and occupies a small chip area when implemented in LSI. <Embodiment> FIG. 6 shows an embodiment of the present invention, in which the line loss compensation SCF 100 and the waveform shaping SCF 200 are connected between the signal input terminal 1 and the equalized waveform output terminal 2, as in the case of FIG. 2. connected in cascade. Capacitive elements C 51 to C 5o are selectively connected as capacitive element 5 by an analog switch, and similarly capacitive elements 6, 7, 9, 10,
Each capacitive element 11 is selectively connected by an analog switch. SCF100 for line compensation, SCF200 for waveform shaping
The transfer functions are expressed by the above equations (1) and (2), respectively, where the capacitance values of the capacitive element groups 5-7 and 9-11 are Ci (i=5-7, 9-11). Also, at this time, Ci is expressed by the following formula. C i = 〓 q k iq C iq (i=5~7, 9~11) (5) In this example, the capacitance value C iq (i=5 ~
7. q=1 to n, k, l,...) are determined as shown below. In the following explanation, for m types of transmission speeds, the maximum loss to be equalized is G decibels,
Although the equalization step is assumed to be ΔG decibels, it can be similarly applied to the case where the maximum loss to be equalized and the equalization step change depending on the transmission speed. Further, the transmission speed to be equalized up to the highest frequency range is called the first transmission speed, and the transmission speed to be equalized up to the mth high frequency range is called the m-th transmission speed. (1) First, n capacitive elements (n=G/ΔG) are prepared in order to equalize the first transmission rate in ΔG steps. (2) Next, capacitive elements for the capacitive elements 5 to 7 are prepared for the portion where the frequency characteristic of the second transmission rate cannot be equalized with the frequency characteristic of the first transmission rate. The maximum frequency to be equalized at the second transmission rate is
1/P 2 of the maximum frequency to be equalized at the transmission speed of
Assuming that, the line loss is generally proportional to the square root of the frequency, so the frequency characteristic that equalizes the first transmission speed can equalize up to 1/√ 2 of the maximum line loss G at the second transmission speed. . Therefore, the unequalized loss range G/√ 2 at the second transmission rate
A capacitive element for equalizing up to G is prepared. Assuming that the number of new capacitive elements to be prepared is N2 , it is expressed by the following equation. (3) Similarly, for the 3rd to mth transmission speeds, the unequaled portions of the frequency characteristics up to the (q-1)th (q = 3 to m) are equalized in steps of △G decibels or less. Prepare a capacitive element so that it can be used. As for the SCF200 for waveform shaping, it is only necessary to change the cutting frequency of the low-pass filter for each transmission speed, so as shown in Figure 6, capacitive element groups 9 to 1 are used.
m capacitive elements C ir (i=9~
11, r=1~m) is prepared, and the capacitive element C ir
Analog switches provided in pairs at both ends of
By switching S ir (i=9 to 11, r=1 to m), m types of cutting frequencies are obtained. SCF for line loss compensation when using this example
(Fig. 6 100), SCF for waveform shaping (Fig. 6 200)
and equalized waveform output terminal 2 from input terminal 1 in FIG.
The overall frequency characteristics up to this point are shown in Fig. 7. FIG. 7 shows an example in which the system can be applied to two types of transmission speeds, where A is the SCF for line loss compensation, B is the SCF for waveform shaping, and C is the overall frequency characteristic. The maximum frequency to be equalized at the q-th transmission rate is 1/ of the maximum frequency to be equalized at the first transmission rate.
Pr, and the numbers of capacitive elements other than the integral capacitive elements of the SCF 100 for line loss compensation and the SCF 200 for waveform shaping are respectively α and β, then for m types of transmission speeds, the line The total number N T of capacitive elements other than the integral capacitive element for equalizing loss is expressed by the following equation. <Effects> In this embodiment, the number of capacitive elements required for the SCF 100 for line loss compensation does not need to increase in proportion to the number of meters of transmission speed to which it is applied, so the number of capacitive elements is smaller than that of the conventional method. It can function as an equalizing amplifier for multiple transmission rates with a small number of analog switches. As an example, Table 1 shows the number of sets of capacitive elements and analog switches required when applicable to two and three types of transmission speeds.
【表】
こゝで第2の伝送速度で等化すべき最大周波数
は第1の伝送速度の1/2、第3の伝送速度で等
化すべき最大周波数は第3の伝送速度の1/3と
し、式(4)、式(6)におけるパラメータでG=40dB、
△G=2dB、n=20、α=3、β=3とした。表
1の例の場合、この実施例を用いれば20〜40%程
度の容量素子の数の低減が可能であり、同様にし
て前記パラメータPr,G,△G,α,βが異な
る場合についてもこの実施例によれば容量素子及
びアナログスイツチの数の低減が可能である。
以上説明したように、この発明によれば従来と
比べ少ない容量素子数、アナログスイツチ数で複
数の伝送速度に適用できるSCF化等化増幅回路を
構成でき、集積回路化を図つた場合、占有面積の
低減を図れる利点がある。またこの発明ではアナ
ログスイツチ配線を少なくできるため、浮遊容量
による精度劣化が小さく、高精度な等化が可能な
利点がある。[Table] Here, the maximum frequency to be equalized at the second transmission rate is 1/2 of the first transmission rate, and the maximum frequency to be equalized at the third transmission rate is 1/3 of the third transmission rate. , the parameters in equations (4) and (6) are G=40dB,
ΔG=2 dB, n=20, α=3, and β=3. In the case of the example in Table 1, it is possible to reduce the number of capacitive elements by about 20 to 40% by using this embodiment, and similarly when the parameters Pr, G, △G, α, β are different, According to this embodiment, the number of capacitive elements and analog switches can be reduced. As explained above, according to the present invention, it is possible to construct an SCF equalization amplifier circuit that can be applied to multiple transmission speeds with a smaller number of capacitive elements and fewer analog switches than in the past, and when integrated, the occupied area is reduced. This has the advantage of being able to reduce Furthermore, since the number of analog switch wirings can be reduced in the present invention, there is an advantage that accuracy deterioration due to stray capacitance is small and highly accurate equalization can be performed.
第1図は線路損失の周波数特性曲線図、第2図
はSCFを用いた等化増幅回路の一般的な構成例を
示す回路図、第3図及び第4図はそれぞれ複数の
伝送速度に対して適用可能な等化増幅回路に用い
られる従来の容量素子群の構成を示す図、第5図
は第3図及び第4図の構成を用いた場合の周波数
特性例を示す図、第6図はこの発明の実施例を示
す回路図、第7図は第6図の回路の周波数特性例
を示す図である。
100:線路損失補償用SCF、200:波形整
形用SCF、1:信号入力端子、2:等化波形出力
端子、3:線路損失補償用SCF出力端子、4〜1
1:容量素子、A1,A2:演算増幅器、S1〜S7:
アナログスイツチ、Cij(i=5〜7、9〜11、j
=1〜n):容量、Sij(i=5〜7、9〜11、j
=1〜n):アナログスイツチ。
Figure 1 is a frequency characteristic curve diagram of line loss, Figure 2 is a circuit diagram showing a general configuration example of an equalization amplifier circuit using SCF, and Figures 3 and 4 are for multiple transmission speeds. FIG. 5 is a diagram showing an example of frequency characteristics when the configurations of FIGS. 3 and 4 are used, and FIG. 7 is a circuit diagram showing an embodiment of the present invention, and FIG. 7 is a diagram showing an example of frequency characteristics of the circuit of FIG. 6. 100: SCF for line loss compensation, 200: SCF for waveform shaping, 1: Signal input terminal, 2: Equalized waveform output terminal, 3: SCF output terminal for line loss compensation, 4 to 1
1: Capacitive element, A 1 , A 2 : Operational amplifier, S 1 to S 7 :
Analog switch, C ij (i=5~7, 9~11, j
=1~n): Capacity, S ij (i=5~7, 9~11, j
=1~n): Analog switch.
Claims (1)
するPCM信号用AGC等化器を、線路の持つ√
f損失特性(周波数fにおける損失が√に比例
する)を補償するため、√特性に近似した離散
的な複数の利得特性を有し、これら特性を半導体
スイツチとキヤパシタと演算増幅器からなるスイ
ツチトキヤパシタ回路で構成し、前記複数の離散
的特性を、使用するキヤパシタをスイツチで切り
換えて実現する損失等化器と、スイツチトキヤ
パシタ回路で構成し、等化の障害になる高周波成
分を取り除く波形整形用低域通過フイルタとの両
者で実現する等化増幅回路において、複数の伝送
システムに適用できるようにするため、等化すべ
き複数の伝送システムの伝送速度のうちで、最も
高い伝送速度を持つシステムの周波数範囲0〜f1
(Hz)に対し、周波数f1にて一定の利得ステツプ
△G(dB)で等化損失範囲0〜G(dB)を等化す
るための第一のキヤパシタ群と、2番目に高い伝
送速度のシステムの周波数範囲0〜f2(Hz)に対
して上記第一のキヤパシタ群で等化不可能な損失
範囲、即ち周波数f2にて損失G/√1〜G(dB)
を周波数f2にて一定の利得ステツプ△G(dB)で
等化する第二のキヤパシタ群と、以下i番目に高
い伝送速度のシステムの周波数範囲0〜fi(Hz)
に対し第i―1番目までのキヤパシタ群で等化不
可能な損失範囲、即ち周波数fiにて損失G/√i-1
〜G(dB)を周波数fiにて一定の利得ステツプ△
G(dB)で等化する第i番目のキヤパシタ群とよ
りなる損失等化器と、カツトオフ周波数がf1′,
f2′…fi′(Hz)(fk′は第k番目に高い伝送速度を
持つシステムのためのカツトオフ周波数)のi通
りに切り換えられるように、i種類のキヤパシタ
群を持つ波形整形用低域通過フイルタとからなる
等化増幅回路。1 An AGC equalizer for PCM signals that adaptively compensates for the line loss and distortion of the signal transmission line is
In order to compensate for the f loss characteristic (loss at frequency f is proportional to √), we have multiple discrete gain characteristics that approximate the √ characteristic, and these characteristics are combined with a switch capacitor consisting of a semiconductor switch, a capacitor, and an operational amplifier. A loss equalizer consists of a circuit and realizes the plurality of discrete characteristics by switching the capacitors used, and a waveform shaping device consists of a switch capacitor circuit and removes high frequency components that interfere with equalization. In order to be able to apply the equalization amplifier circuit to multiple transmission systems, which is realized by both the low-pass filter and the low-pass filter, the system with the highest transmission speed among the multiple transmission systems to be equalized is Frequency range 0~ f1
(Hz), the first capacitor group for equalizing the equalization loss range 0 to G (dB) with a constant gain step △G (dB) at frequency f 1 , and the second highest transmission rate. The loss range that cannot be equalized by the first capacitor group for the frequency range 0 to f 2 (Hz) of the system, that is, the loss G/√ 1 to G (dB) at frequency f 2
a second group of capacitors that equalizes with a constant gain step △G (dB) at frequency f 2 and the following frequency range 0 to f i (Hz) of the system with the i-th highest transmission rate.
The loss range that cannot be equalized in the i-1st capacitor group, that is, the loss G/√ i-1 at frequency f i
~G (dB) at a constant gain step △ at frequency f i
A loss equalizer consisting of an i-th capacitor group that equalizes by G (dB), and a cut-off frequency of f 1 ′,
f 2 ′...f i ′ (Hz) (f k ′ is the cutoff frequency for the system with the kth highest transmission rate) for waveform shaping with i types of capacitor groups so that it can be switched in i ways Equalization amplifier circuit consisting of a low-pass filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16176782A JPS5950607A (en) | 1982-09-16 | 1982-09-16 | Equalizing amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16176782A JPS5950607A (en) | 1982-09-16 | 1982-09-16 | Equalizing amplifying circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5950607A JPS5950607A (en) | 1984-03-23 |
| JPS6366451B2 true JPS6366451B2 (en) | 1988-12-20 |
Family
ID=15741507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16176782A Granted JPS5950607A (en) | 1982-09-16 | 1982-09-16 | Equalizing amplifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5950607A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62167221A (en) * | 1986-01-17 | 1987-07-23 | Showa Denko Kk | Production of lepidocrocite |
| JP2009530897A (en) * | 2006-03-17 | 2009-08-27 | Nsc株式会社 | Composite BPF and orthogonal signal filtering method |
-
1982
- 1982-09-16 JP JP16176782A patent/JPS5950607A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5950607A (en) | 1984-03-23 |
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