JPS6366455B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the configuration of a counting circuit for counting digital pulses.

Conventionally, a counter circuit for counting a certain number is configured as shown in FIG. That is, if a clock pulse Cl is applied to the counter circuit 1 (for example, a fully synchronous counter IC manufactured by Texas Instruments, SN74163N, etc.), the counter output will be 0, 1, 2, . . . n, n+1, . . . Increases by 1 at the rising edge of clock Cl. If the clear input Cr is applied for one clock period, the counter output will be forced to 0, then 1, 2, etc.
3. Continue counting again as follows. Therefore,
If a clear pulse is applied at a certain period, the counter output will repeat counting at a certain period. Here, if the clear input Cr is always stable, the counter output also operates stably.

However, when applied to actual equipment, it is not always possible to obtain clear input stably. In some cases, the phase of the clear input may shift, and the clear input itself may be disconnected. In such a case, the counter circuit may malfunction, resulting in an undesirable state for the device.

The present invention has been made to eliminate the above-mentioned drawbacks of the conventional art, and therefore, an object of the present invention is to provide a novel circuit that can continue counting normally even in the above-mentioned cases. It turns out.

In order to achieve the above object, the present invention inhibits the clear input using a pulse obtained by decoding the output of the counter circuit when the phase of the clear input is shifted, so as to prevent malfunction. The output from another decoder circuit configured to clear the counter circuit with the correct phase is supplied to the clear terminal.

That is, according to the present invention, the pulse counting circuit includes a first decoding circuit that decodes the count output by a predetermined number, and an output of the first decoding circuit that receives a reset signal from the outside to the counting circuit. A stabilizing count circuit comprising: a prohibition circuit; a second decode circuit that decodes with a predetermined number; and a circuit that resets a count circuit with the output of the second decode circuit. is obtained.

Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, the clear input Cr becomes one input of an AND circuit (the AND circuit in FIG. 2 is a negative input AND circuit as an example). AND
A pulse obtained by inverting the polarity of the pulse obtained by decoding the counter 11 by a decoding circuit (decoder) 12 by an inverter INV is applied to the other input of the circuit. The output of the AND circuit is applied as an input to the OR circuit, and the output of the decoding circuit (decoder) 13 is applied to the other input of the OR circuit. The output of the OR circuit is added to the clear input of the counter 11.

Here, it is assumed that the counter circuit according to the present invention is configured to repeatedly count from 0 to N, for example. Third clear input Cr
As shown in Figure a, this is a pulse train with a period of N+1 clock length. b indicates the clock input Cl, and c indicates the numerical value of the output of the counter 11. d is the output of the decoding circuit 13, which outputs a pulse only when the output value of the counter 11 is N. e is the output of the decoding circuit 12, which outputs a pulse only when the output value of the counter 11 is N-1. The output of the decode circuit 12 is inverted in polarity by the inverter INV and then applied to the above-mentioned AND gate circuit. Therefore, the clear input Cr is prohibited during the period when the output of the decoding circuit 12 exists, that is, during the period when the counter output value is N-1. In other words, the phase of the clear input Cr may change as shown in Fig. 3 for some reason.
If it advances forward as shown in the dotted line portion of a', the advanced portion is inhibited and the output of the AND gate circuit becomes as shown in diagram f. In this case, depending on the extent to which the phase advances, there may be a remaining "scrap" as shown in the center of the diagram f, but this part does not cross the rising edge of the clock Cl in b, so the clearing operation will not occur in this part. No. Therefore, in this case, the pulse from the decoding circuit 13 is supplied to the OR gate circuit,
Since this gate circuit output is applied to the clear terminal of the counter 11, the counter 11 is cleared to a normal value and continues counting normally.

In this way, an incorrect clear input is inhibited by the output of the decoding circuit 12, and the counter 11 is instead cleared by a pulse from the decoding circuit 13, so even if the clear input has a slight phase shift, it will count correctly. can continue.

Here, the decoding circuit 12 assumes that the counter value is N
Although we have proceeded with the discussion assuming that the output is generated only when the clock is -1, for example, it is possible to configure the output so that it is also output when the clock is N-2. In this case, the clear input will be advanced by two clocks. It is clear that the count can continue correctly even if the This amount can be determined in practical applications from the expected phase shift of the clear input.

Furthermore, in this embodiment, a clear input is applied to the clear terminal to reset the counter value, but it goes without saying that other methods may be used as long as the counter value can be regulated. . It goes without saying that the present invention can be implemented with various modifications without departing from its scope.

As explained above, according to the present invention, by combining a counter, a decoder, an AND gate circuit, and an OR gate circuit as described above, a stable counter circuit can be realized even when there is a phase shift (jitter) in the clear input. can be configured.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional counter circuit, FIG. 2 is a block configuration diagram showing an embodiment of the stabilizing counter circuit according to the present invention, and FIG. 3 is a diagram showing the timing of each part used for explaining FIG. 2. It is. 1, 11...Counter, 12, 13...Decoding circuit (decoder).

Claims (1)

[Claims] 1 In the pulse count circuit, the first circuit decodes the count output with a predetermined number.
a decoding circuit, a circuit for prohibiting a reset signal from the outside to the counting circuit by the output of the first decoding circuit, a second decoding circuit for decoding with a predetermined number, and the second decoding circuit. A stabilizing count circuit comprising: a circuit for resetting the count circuit at the output of the circuit.