JPS6367143B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency measurement method that divides a possible display area and displays counts at different gate times in each of the divided display areas.

Generally, speedometers and engine tachometers installed in automobiles do not calculate and display measurement signals input from a detection unit as they are, but display them after being corrected by a certain percentage. For example, in the case of a speedometer, the index error when indicating the traveling speed must be within the range specified in the "Safety Standards for Road Transport Vehicles." In general, each vehicle type has its own index standard within the range that satisfies the above regulations, and in most cases, a negative indication is given in a low speed range and a positive indication is given in a high speed range.

This is because the actual vehicle speed does not necessarily match the rotational speed of the axle on which the detection unit is installed due to tire deformation, slippage, etc., and is set to have a positive tendency, including from the viewpoint of safety at high speeds.

For example, in order to obtain a display that has been corrected for each speed range as shown in Figure 1, conventional general-purpose pointer type overcurrent meters have a scale on the dial corresponding to the rotational speed of the transmission cable. Processing such as printing on a negative side is applied.

However, the pulse counting type digital speedometers that have been adopted in recent years are configured to count and display according to the gate time set in advance according to the display resolution, so it is not possible to faithfully measure the measurement signal from the detection unit in the entire display area. Only counts can be obtained, and in order to make these conform to the required index standards, calculation processing must be performed to add appropriate corrections to the counts.
This has the disadvantage that the processing from detection to display is complicated.

Furthermore, in such a gate time type frequency meter, in order to improve responsiveness to changes in the measured quantity, the reference gate time set according to the display resolution is divided into multiple divisions, and the count values in this division period are sequentially calculated. A configuration is proposed in which the pulses are shifted to the next register and the number of pulses corresponding to the reference gate time is added and output at the above-mentioned division period. This results in problems such as the processing becomes complicated, the calculation processing speed is fast, and expensive circuits must be used.

Also, in order to prevent overspeeding in the high speed range, it may be necessary to correct the engine tachometer to display a positive trend, and even when displaying this digitally, it may have the same problem as the speedometer. Become.

In order to eliminate the drawbacks of the conventional example, the present invention divides a reference gate time into a plurality of gate times, calculates the count value at the reference gate time for each divided gate time, and displays at least one of the divided possible display areas. The gate time in the area is set as a correction gate time that increases or decreases by a slight correction time length from the reference gate time, and the count content at the reference gate time or any correction gate time can be displayed in multiple display areas by dividing the display area. It is characterized by determining which area corresponds to the display area, and latching and displaying the count value at the reference gate time or corrected gate time corresponding to the display area based on the determination result, and its purpose is to latch and display the count value at the reference gate time or corrected gate time corresponding to the display area based on the determination result. The purpose of this invention is to provide a frequency that allows corrected display according to the display area to be performed with good responsiveness for the actual measured quantity. Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 shows a block diagram of a frequency meter according to one embodiment of the present invention, in which 1 is a pulse input terminal, 2 is a pulse input terminal;
is the first counter, 3 ₁ , 3 ₂ , 3 ₃ are the first, second,
3rd register, 4 is adder, 5 is latch circuit,
6 is a decoder driver, 7 is a display, 8 is a comparator, 9 is a memory that stores a predetermined area determination value, 10 is a selection circuit that selects the count content in a predetermined correction time length, and 11 is a 1 is a timer, 12 is a one-shot multi, 13 is a second timer, 14 is a second counter, 15 is a third timer, 16 is a third counter, and 17 is an OR gate.

Next, the operation of this embodiment will be explained. First, pulses input from the pulse input terminal 1 are counted by the first counter 2, and the output from the first timer 11 determines one gate time T (for example,
Cleared by a pulse output from the one-shot multi 12 every divided gate time (200 msec) divided into 1/3 of 600 msec), the first, second, and third registers 3 ₁ , 3 ₂ , 3 ₃ By issuing a load pulse, the number of pulses at a divided gate time corresponding to 1/3 of the gate time (hereinafter referred to as reference gate time) T is sequentially increased to the first, second, and third registers 3 ₁ , 3 ₂ , 3 ₃ (see Figure 3). The contents of these first, second, and third registers 3 ₁ , 3 ₂ , and 3 ₃ are the load pulses output from the OR gate 17 based on the output pulses of the one-shot multi, and are used as the number of pulses at the reference gate time T for the adder. 4 is added. Therefore, the criterion T
The number of pulses in is calculated every 1/3 division period,
The contents of this adder 4 are compared in a comparator 8 with the area determination value stored in a memory 9. Here, when the output of the adder 4 is in the area A in FIG. be done.

Further, when the output of the adder 4 is in the area B in FIG. 1, the selection circuit 10 selects the count value of the second counter 14. After this second counter 14 is cleared by a pulse from the one-shot multi 12, the timer 13 counts the pulses input from the pulse input terminal 1 for a predetermined correction time length, for example, 2 msec. Therefore, as shown in FIG. 3, the output of the second counter 14 is a correction time length T ₁ from the end of one reference gate time T.
(during 2msec) is the number of pulses counted.
The output of the second counter 14 is selected by the selection circuit 10, inputted to the adder 4, and shifted to the first, second, and third registers ₃₁ , ₃₂ , and ₃₃ . It is added together with the pulse number 0, that is, the pulse number corresponding to the reference gate time. The output of the adder 4 is latched by the latch circuit 5 by the load pulse of the comparator 8, and is displayed on the display 7.

Also, if the output of adder 4 is in area C,
The count value of the third counter 16 is selected by the selection circuit 10. Similarly to the second counter 14, this third counter 16 is also one-shot multi 12
After being cleared by the output pulse of , the correction time length T ₂ determined by the timer 15 as shown in FIG.
For example, the pulses input from the pulse input terminal are counted for only 4 msec. Therefore, the output of the third counter 16 is calculated by the correction time length T from the end of one reference gate time T as shown in FIG. This is the number of pulses counted during ₂ . The output of the third counter 16 is selected by the selection circuit 10 and inputted to the adder 4,
The contents of registers 3 ₁ , 3 ₂ , and 3 ₃ are added.
The output of the adder 4 is latched by the latch circuit 5 by the load pulse from the comparator 8, and is displayed on the display 7.

Since the present embodiment is configured in this way, it is possible to easily determine the correction value at the correction gate time according to the divided areas A, B, and C according to the display area determination result.

Note that in the above embodiment, the display is corrected by adding the correction time length _T1 or _T2 to the reference gate time T for areas B and C, but the correction time length corresponding to area A is set. However, by providing a counter and a timer to obtain the number of pulses during this period, it is possible to correct the display in each of areas A, B, and C as shown in FIG.

FIG. 5 is a block diagram of a frequency meter according to another embodiment of the present invention in which the display is corrected in areas A, B, and C, and the area is determined again based on the count value at the corrected gate time. is a pulse input terminal, 2 is a counter, 3 is a register, 4 is an adder, 5 is a latch circuit, 6 is a decoder driver, 7
is a display, 8 is a comparator, 9 is a memory, 10 is a selection circuit, 11 is a first timer, 12 is a one shot multi, 13 is a second timer, 14 is a second counter, 15 is a third timer , 16 is the third counter, 17 is the OR gate, and these devices are the second counter.
Since the operation is the same as that of the embodiment shown in the figure, the explanation will be omitted. It is provided in parallel with the counters 14 and 16 and connected to the selection circuit 10. Note that 20 is a counter for setting the region determination ranking.

In this embodiment, as shown in FIG. 6, even in region A of FIG.
By adding T ₁ , the number of corrected pulses can be added to the actual number of pulses.The most important feature is that the display area is determined again based on the number of pulses at the corrected gate time, and the number of corrected pulses is determined based on the number of pulses at the corrected gate time. The object is to be latched and displayed only when the judgment result is in the corresponding area. As an example,
A case in which display areas A, B, and C are determined in this order will be described as follows. First, the clear output of the counter 20 causes the selection circuit 10 to select the output of the second counter 14 . The adder 4 adds the number of pulses counted by the counter 14 to the sum of the registers 3 ₁ , 3 ₂ , 3 ₃ and the corrected time length T ₁ of the second timer 13 (see FIG. 6). The content of this adder 4 is compared with the area determination value of area A in comparator 8, and if it is within area A, a load pulse is output from comparator 8, and the added value of adder 4 is transferred to the latch circuit. It is latched at 5 and displayed on display 7.

Next, if the content of the adder 4 does not fall within the area A in FIG. In the selection circuit 10,
The third counter 16 corresponding to area B is controlled by the control signal corresponding to the count "1" of the counter 20.
The number of pulses counted in is selected. This counter 16 is the number of pulses counted during the correction time length T ₂ (see FIG. 6), which is the output of the third timer 15, and this number of pulses is passed through the selection circuit 10 to the adder circuit ₄ , It is added to the sum of 3 ₂ and 3 ₃ . The contents of this adder 4 are again compared by the comparator 8 with the area determination value of area B in FIG. The added value of the unit 4 is latched by the latch circuit 5 and displayed on the display 7.

Furthermore, if the added value of the adder 4 does not fall within the region B, the number of pulses counted by the fourth counter 19 is selected by the selection circuit 10 controlled by the control output of the counter 20. This counter 19 is the number of pulses counted during the correction time length T ₃ (see FIG. 6), which is the output of the fourth timer 18.
This number of pulses is determined by the addition circuit 4 through the selection circuit 10.
It is added to the sum of registers 3 ₁ , 3 ₂ , and 3 ₃ at . The contents of the adder 4 are again compared with the area determination value of the memory 9 by the comparator 8, but since the contents are in the area C in FIG. The added value is latched by the latch circuit 5 and displayed on the display 7.

Since the present embodiment is configured in this way, the correction corresponding to the display area determined based on the latest count value is always performed, thereby enabling more accurate corrected display.

In the above embodiment, one reference gate time T
Although the adder 4 adds the number of pulses in the corrected time length set from the end of the reference gate time T, it is also possible to add the counted pulses to the corrected time length set before the reference gate time T starts.

FIG. 7 is a block diagram of a frequency meter according to still another embodiment of the present invention. Portions with the same symbols as those in FIG. , 19 in series with registers 21 ₁ , 21 ₂ , 21 ₃ , registers 22 ₁ ,
22 ₂ , 22 ₃ and registers 23 ₁ , 23 ₂ , 23 ₃ are connected.

This embodiment differs from the embodiment shown in FIG.
As shown in the figure, the correction time length corresponding to each area A, B, and C before one reference gate time T starts
One of T ₁ , T ₂ , and T ₃ is added.
That is, when the second timer 13 is cleared and started by the output of the one-shot multi 12 when the divided gate time Td immediately before one reference gate time T starts, the second timer 13 starts at the time t ₁ at one divided gate time Td. Correction time length after 198msec
The output pulse is output for T ₁ , that is, 2 msec, during which time the counter 14 counts the pulses input from the pulse input terminal 1. The counted pulses are sequentially shifted to the registers 21 ₁ , 21 ₂ , 21 ₃ by the load pulses output from the one-shot multi 12 at every division gate time Td. Similarly, when the third timer 15 is cleared and started by the output of the one-shot multi 12 when the divided gate time Td immediately before one reference gate time starts, the third timer 15 starts one divided gate time.
At Td, after a time t ₂ , i.e. 196 msec, an output pulse is issued for a correction time length T ₂ , i.e. 4 msec;
During this time, the counter 16 counts the pulses input from the pulse input terminal 1. The counted pulses are sequentially shifted to the registers 22 ₁ , 22 ₂ , and 22 ₃ by the load pulses output from the one-shot multi 12 at every division gate time Td. Further, when the fourth timer 18 is cleared and started by the output of the one-shot multi 12 when the divided gate time Td immediately before one reference gate time T starts, the fourth timer 18 starts at the time t ₃ at one divided gate time Td. That is, after 194 msec, an output pulse is issued for a correction time length T ₃ , that is, 6 msec,
During this time, the counter 19 counts the pulses input from the pulse input terminal 1. The counted pulses are sequentially shifted to the registers 23 ₁ , 23 ₂ , and 23 ₃ by the load pulses output from the one-shot multi 12 at every division gate time Td. The correction values shifted in this way and placed in the registers 21 ₃ , 22 ₃ , and 23 ₃ respectively are selected for each area A, B, and C by the selection circuit 10 with the same judgment operation as in the embodiment shown in FIG. As a result, it is possible to display images as shown by solid lines in areas A, B, and C shown in FIG. 4, respectively.

In addition, in the frequency meter of the above-mentioned embodiment, the number of corrected pulses is added, but if the actual measured value is to be corrected and displayed with a negative tendency, the number of corrected pulses is added from the sum of registers 3 ₁ , 3 ₂ , and 3 ₃ Needless to say, this can be achieved by subtracting the number of correction pulses corresponding to the correction time length.

As explained above, according to the present invention, a reference gate time is divided into a plurality of gate times, a count value at the reference gate time is obtained for each divided gate time, and a possible display range is divided into a plurality of display areas. Then, the gate time in at least one area of this display area is set as a corrected gate time that is increased or decreased by a slight correction time length from the reference gate time, and the counting contents at the gate time corresponding to each area are calculated. Therefore, for example, it is possible to perform a correction display corresponding to the index characteristic area defined for each vehicle type with good responsiveness, and an extremely reliable frequency meter can be obtained.

[Brief explanation of drawings]

Figure 1 is a diagram showing the correction characteristics of displayed values with respect to actual measured values by divided display area, Figure 2 is a block diagram of a frequency meter according to an embodiment of the present invention, and Figure 3 is a reference gate time and correction gate time. FIG. 4 is a diagram showing a state in which the possible display area is divided and displayed. FIG. 5 is a block diagram of a frequency meter according to another embodiment of the present invention. FIG. 6 is a diagram showing a reference gate. FIG. 7 is a block diagram of a frequency meter according to another embodiment of the present invention, and FIG. 8 is a diagram showing the relationship between the reference gate time and the corrected gate time. FIG. 1... Pulse input terminal, 2... Counter, 3 ₁ , 3
₂ , 3 ₃ ... Register, 4... Adder, 5... Latch circuit, 6... Decoder driver, 7... Display, 8... Comparator, 9... Memory, 10... Selection circuit, 11, 1
3,15,18...Timer, 12...One shot multi, 14,16,19...Counter, 17...OR gate, 20...Counter, 21 ₁ , 21 ₂ , 21 ₃ ,
22 ₁ , 22 ₂ , 22 ₃ , 23 ₁ , 23 ₂ , 23 ₃ ... register.

Claims (1)

[Claims] 1 Divide the reference gate time into multiple gate times, count the input pulse signal for each divided gate time, add the counts at each divided gate time, and find the total count equivalent to the standard gate time for each divided gate time. At the same time, the possible display range is divided into a plurality of display areas, and the gate time in at least one of these display areas is set as a correction gate time that increases or decreases by a slight correction time length with respect to the reference gate time, and the correction time By counting input pulse signals corresponding to the length independently before or after the reference gate time, and adding or subtracting the counted value corresponding to the corrected time length to the counted value equivalent to the reference gate time, the calculated value corresponds to the corrected gate time. A frequency measurement method characterized by obtaining a count value of.