JPS6367276B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a magnetic bubble memory element used as a storage device for electronic computing devices and the like.

Conventional technology and problems Conventionally, in magnetic bubble memory devices, functional units that switch transfer paths, divide bubble domains, etc. are configured to utilize the local magnetic field generated when a pulse current is passed through a conductor wire. but,
The rotation of the conductor pattern that supplies the pulsed current at this time is one of the factors that increases the chip size. FIG. 4 shows the structure of a conventional magnetic bubble memory chip having an even/odd structure. In the figure, A is an even block, B is an odd block, 30 and 30' are generators, 31 and 31' are major lines for writing, 32 _-1 to 32 _-o , 32' _-1 to 32' _-o are swap gates, and 33 , 33' are its conductor patterns, 34 _-1 to 34 _-o and 34' _-1 to 34' _-o are minor loops, 35 _-o to 35 _-1 , 35' _-o to 35' _-1
denotes a replicate gate, 36 and 36' its conductor patterns, 37 and 37' a readout major line, and 38 a detector, respectively. In a bubble memory chip having such a structure, the replicator conductors 36 and 36', which use relatively large pulse currents, are divided into upper and lower parts and folded back to reduce the load. Also swap gate conductor 33,3
3' is folded back to balance the number of bonding pads at the top and bottom of the chip. FIG. 5 is an enlarged view of these turning points, where a shows the replicator part and b shows the swap gate part, respectively.
In the figure, 40 is a gate conductor pattern;
41 indicates a permalloy pattern.

Conventional magnetic bubble memory devices require a considerable amount of space due to the conductor crawling described above, which increases the chip size, leading to problems such as increased cost and increased driving voltage. Ta.

OBJECTS OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a magnetic bubble memory element in which the rotation of gate conductor patterns is rationalized and an increase in chip size is suppressed.

Structure of the Invention According to the present invention, there is provided a magnetic bubble memory element in which division and transfer of bubble domains is controlled by passing a pulse current through a gate conductor pattern, in which the conductor patterns are arranged such that at least a portion thereof overlaps with each other. A magnetic bubble having a two-layer structure with an insulating layer sandwiched between the two layers, and conductor patterns above and below the folding point are connected via a through hole provided in the insulating layer. This is achieved by providing a memory element.

Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view illustrating a magnetic bubble memory device according to the present invention.

In the figure, 1 is a GGG substrate, 2 is a garnet crystal for bubbles, 3 is a first spacer layer, and 4 is a second spacer layer.
5 is a spacer layer, 5 is a third spacer layer, 6 is a lower gate conductor pattern, 7 is a permalloy pattern, 8 is a through hole, and 9 is an upper gate conductor pattern.

In this embodiment, as shown in FIG. 1, a first spacer layer 3, a lower gate conductor pattern 6 constituting the gate, a second spacer layer 4, a permalloy pattern 7, and a third spacer layer 5 are formed on the garnet crystal 2 for bubbles. After sequentially laminating the layers, a through hole 8 is formed at a predetermined position through the second and third spacers, an upper conductor pattern 9 is formed so as to overlap the lower gate conductor pattern 6, and the upper conductor pattern 9 is formed through the through hole 8 to overlap the lower gate conductor pattern 6. , the lower conductor patterns 6 and 9 are connected.

As described above, in this embodiment, by performing the two-layer wiring of the gate conductor pattern, it is possible to save the space conventionally occupied by the conductor pattern which is folded back in a plane.

FIG. 2 is a plan view showing an example in which the present invention is applied to a replicate gate section. In the same figure, 1
0 is the minor loop, 11 is the major line for readout, 12 is the lower gate conductor pattern,
Reference numeral 13 indicates an upper gate conductor pattern, and reference numeral 14 indicates a through hole.

Conventionally, in order to reduce the resistance value in replicate gates, a method has been used in which the conductor pattern is folded back and divided in the middle as shown in Figure 5a.
In this case, the chip area increases in the lateral direction due to the arrangement of the folded line of the conductor pattern, but in this embodiment, as shown in FIG. By connecting the gate conductor pattern 13 with the through hole 14 at its end, the area of the folded line shown in FIG. 5a can be saved.

FIG. 3 is a plan view showing an example in which the present invention is applied to a swap gate section. In the figure, 20 is a minor loop, 21 is a major line for writing, 22 is a lower gate conductor pattern, 23
24 indicates an upper conductor pattern, and 24 indicates a through hole.

Conventionally, in a magnetic bubble memory element having the configuration shown in FIG. 4, the conductor is folded back at the end of the swap gate as shown in FIG. 5b in order to balance the number of terminals at the top and bottom of the chip. By connecting the lower gate conductor pattern 22 and the upper conductor pattern 23 at their ends through through holes as shown in FIG. 3, the area of the folded line portion shown in FIG. 5b is saved.

Effects of the Invention As described above in detail, the magnetic bubble memory element of the present invention has a great effect of preventing an increase in chip area by using a two-layer wiring for its gate conductor pattern.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a magnetic bubble memory element according to the present invention, FIGS. 2 and 3 are diagrams for explaining an application example of the present invention, and FIG. 4 is a diagram for explaining a conventional even/odd type magnetic bubble memory element. FIG. 5 is a diagram showing the layout of a bubble memory element, and is an enlarged view of its replicate gate and swap gate sections. In the drawing, 1 is a GGG substrate, 2 is a garnet crystal for bubbles, 3 is a first spacer layer, and 4 is a second spacer layer.
Spacer layer, 5 is the third spacer layer, 6, 12, 2
2 is a lower gate conductor pattern, 7 is a permalloy pattern, 8, 14, 24 are through holes,
9, 13, and 23 indicate upper conductor patterns, respectively.

Claims (1)

[Claims] 1. In a magnetic bubble memory element that performs division and transfer control of bubble magnetic domains by applying a pulse current to a gate conductor pattern, the conductor pattern is folded back so that at least a portion thereof overlaps, and an insulating layer is sandwiched between the two conductor patterns. 1. A magnetic bubble memory element configured in a layered structure, and characterized in that conductor patterns above and below a folding point are connected via a through hole provided in an insulating layer.