JPS636740U - - Google Patents
Info
- Publication number
- JPS636740U JPS636740U JP9983786U JP9983786U JPS636740U JP S636740 U JPS636740 U JP S636740U JP 9983786 U JP9983786 U JP 9983786U JP 9983786 U JP9983786 U JP 9983786U JP S636740 U JPS636740 U JP S636740U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- fuse
- measures
- electrostatic damage
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図は本考案の半導体装置の実施例を示す正
面図、第２図は本考案の他の実施例を示す斜視図
、第３図は従来の半導体装置の実施例を示す回路
図、第４図は従来の半導体装置の他の実施例を示
す斜視図である。
３……本考案のＭＯＳトランジスタ、４……本
体、６……ドレイン端子、７……ゲート端子、８
……ソース端子、９……ヒーズ。
FIG. 1 is a front view showing an embodiment of a semiconductor device of the present invention, FIG. 2 is a perspective view showing another embodiment of the present invention, and FIG. 3 is a circuit diagram showing an embodiment of a conventional semiconductor device. FIG. 4 is a perspective view showing another embodiment of the conventional semiconductor device. 3... MOS transistor of the present invention, 4... Main body, 6... Drain terminal, 7... Gate terminal, 8
...Source terminal, 9...Head.
Claims (1)
するヒユーズを取付けて該電極端子間を短絡させ
たことを特徴とする静電破壊防止対策を施した半
導体装置。 (2) 上記ヒユーズが本体の樹脂モールド内にパ
ツケージされたことを特徴とする実用新案登録請
求の範囲第１項記載の静電破壊防止対策を施した
半導体装置。 (3) 上記ヒユーズが外部電極端子間に取付けら
れたことを特徴とする実用新案登録請求の範囲第
１項記載の静電破壊防止対策を施した半導体装置
。 (4) 上記ヒユーズがその半導体装置に印加され
るバイアス電源によつて溶断されるようにしたこ
とを特徴とする実用新案登録請求の範囲第１項乃
至第３項記載の静電破壊防止対策を施した半導体
装置。[Claims for Utility Model Registration] (1) A semiconductor device with measures to prevent electrostatic damage, characterized in that a fuse that blows with a weak current is attached between the electrode terminals of the semiconductor device to short-circuit the electrode terminals. . (2) A semiconductor device with measures to prevent electrostatic damage as set forth in claim 1, wherein the fuse is packaged within a resin mold of the main body. (3) A semiconductor device provided with measures to prevent electrostatic damage as set forth in claim 1 of the utility model registration, characterized in that the fuse is installed between external electrode terminals. (4) The measures for preventing electrostatic damage according to claims 1 to 3 of the utility model registration claim, characterized in that the fuse is blown by a bias power supply applied to the semiconductor device. Semiconductor device processed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9983786U JPS636740U (en) | 1986-07-01 | 1986-07-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9983786U JPS636740U (en) | 1986-07-01 | 1986-07-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS636740U true JPS636740U (en) | 1988-01-18 |
Family
ID=30969087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9983786U Pending JPS636740U (en) | 1986-07-01 | 1986-07-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS636740U (en) |
-
1986
- 1986-07-01 JP JP9983786U patent/JPS636740U/ja active Pending