JPS636744U - - Google Patents
Info
- Publication number
- JPS636744U JPS636744U JP10033786U JP10033786U JPS636744U JP S636744 U JPS636744 U JP S636744U JP 10033786 U JP10033786 U JP 10033786U JP 10033786 U JP10033786 U JP 10033786U JP S636744 U JPS636744 U JP S636744U
- Authority
- JP
- Japan
- Prior art keywords
- flat
- frit seal
- semiconductor container
- joined
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 5
- 239000000758 substrate Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図乃至第３図は本考案の実施例を示す正面
断面図である。
１，２４：多層セラミツク基板（ピングリツド
アレイ部）、４，２３：ガラスフリツト（フリツ
トシール）、５，２２：フラツトリード、２１：
多層セラミツク基板（フラツトパツケージ部）。
1 to 3 are front sectional views showing an embodiment of the present invention. 1, 24: Multilayer ceramic substrate (pin grid array part), 4, 23: Glass frit (frit seal), 5, 22: Flat lead, 21:
Multilayer ceramic substrate (flat package part).
Claims (1)
のピンを植設すると共に、該容器本体の他面に複
数のフラツトリードを配設した半導体容器におい
て、ピングリツドアレイ部とフラツトパツケージ
部とをフリツトシール法により一体接合したこと
を特徴とする半導体容器。 (2) ピングリツドアレイ部がセラミツク回路基
板により構成され、該基板上にフラツトリードを
フリツトシール法により接合したことを特徴とす
る実用新案登録請求の範囲第１項記載の半導体容
器。 (3) フラツトパーケージ部にフラツトリードを
フリツトシールにより接合し、その上にピングリ
ツドアレイ部をフリツトシール法により接合した
ことを特徴とする実用新案登録請求の範囲第１項
記載の半導体容器。[Scope of Claim for Utility Model Registration] (1) A semiconductor container in which a plurality of pins serving as leads are implanted on one side of the semiconductor container body and a plurality of flat leads arranged on the other side of the container body, A semiconductor container characterized in that a lay part and a flat package part are integrally joined by a frit seal method. (2) The semiconductor container according to claim 1, wherein the pin grid array portion is constituted by a ceramic circuit board, and flat leads are bonded to the board by a frit seal method. (3) The semiconductor container according to claim 1 of the utility model registration, characterized in that a flat lead is joined to a flat package part by a frit seal, and a pin grid array part is joined thereon by a frit seal method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10033786U JPS636744U (en) | 1986-06-30 | 1986-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10033786U JPS636744U (en) | 1986-06-30 | 1986-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS636744U true JPS636744U (en) | 1988-01-18 |
Family
ID=30970068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10033786U Pending JPS636744U (en) | 1986-06-30 | 1986-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS636744U (en) |
-
1986
- 1986-06-30 JP JP10033786U patent/JPS636744U/ja active Pending
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