JPS6367776B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer that automatically equalizes linear distortion in a transmission system on the receiving side by using a reference signal waveform that periodically exists in a received signal.

A ghost canceling device for a television receiver is known as one application example of this type of automatic equalizer. Figure 1 shows a known example of a ghost canceling device using a tap delay line filter with variable tap gain. This uses the differential waveform of the part that moves to the 4th line).

In FIG. 1, reference numeral 1 denotes a tapped delay line filter with variable tap gain, which is composed of a tapped delay element 1a, a weighting circuit 1b, and an adding circuit 1c. The delay time T between taps of the delay element 1a with taps is selected to be a value smaller than the reciprocal of twice the highest frequency of the input video signal, for example, 0.1 μs. The total number of taps is determined depending on the delay time range of the ghost to be erased. Among these taps, the tap through which the input signal passes with a relative time delay of 0 is called the main tap. The output of this main tap is branched into two branches, one of which is directly input to the adder circuit 1c. The other is weighting circuit 1
The signal is multiplied by tap gain c _p by b and is input to an adder circuit 1c. In front of the main tap (in the negative direction of relative delay), there are M taps (tap gains c _-M , c _-M+1 ,
...c _-1 ), and there are N taps (tap gains c ₁ , c ₂ ...c _N ) at the rear (in the positive direction of relative delay). In such a delay line filter 1 with taps, the tap gain of each tap (c _{- M} , ..., c _O , ...,
By setting c _N ) to an appropriate value, the ghost that existed at the input terminal 20 is substantially eliminated at the output terminal 30. The tap gain can be automatically controlled to minimize the ghost component of the output as follows.

First, among the video signals introduced into the tap delay line filter 1 via the input terminal 20, a signal with a relative delay O appearing at the main tap is input to the timing circuit 11.
is introduced, thereby setting the time reference of the system in the timing circuit 11. This time reference is set so that the peak position of the differential waveform of the leading edge of the vertical synchronization waveform of the output signal of the main tap is the time origin (t=0). In the timing circuit 11, this t
A clock with period T is created with =0 as the reference point.

The reference waveform generation circuit 3 is a circuit that generates an ideal reference waveform r(t) corresponding to the differential waveform of the vertical synchronization waveform assuming that no ghost originally exists, and is, for example, an impulse generation circuit.
Consists of LPE. The peak of the reference waveform r(t) generated here is the peak of the timing circuit 11.
This corresponds exactly to t=0 set in .

The video signal that has passed through the tapped delay line filter 1 is output to an output terminal 30 and is also introduced into a difference circuit 4 via a differentiation circuit 2. This differential circuit 2
Let the output of y(t) be y(t). Although the waveform obtained by differentiating the output signal of the main tap does not appear directly, this waveform is designated as x(t) and will be referred to as the input waveform hereinafter. Also,
y(t) is called an output waveform. In the difference circuit 4, the reference waveform r(t) is subtracted from the output waveform y(t),
It is output as an error waveform e(t).

The relationship among x(t), y(t), and e(t) can be expressed mathematically as follows.

y(t)=x(t)+ _N 〓 ^i=-M c _i x(t-iT)...(1) e(t)=y(t)-r(t)...(2) 1st The automatic equalizer shown in the figure has a tap gain {c _i }
It operates to correct (i=-M,...,N).

The error waveform e(t), which is the output of the difference circuit 4, is
The A/D converter 5 encodes the data. A/D converter 5
A sampling clock with a period T is supplied from the timing circuit 11. The sample value e(kT) of the error waveform e(t) sampled at time t=kT is abbreviated as e _k . (Hereafter, x _k , y _k , r _k
etc. are used in the same meaning) e _k is multiplied by a negative constant −α in the coefficient circuit 6 and then supplied to one input terminal of the adder circuit 7 .

Tap gain memory 8 is a digital memory of (M+N+1) words, and tap gain {C _k }(-
MkN) is stored. {c _k } is read out from this memory 8 in the order of c _-M , c _-M+1 . . . and supplied to the other input terminal of the adder circuit 7 . The adder circuit 7 performs a digital operation expressed by the following equation.

c ⁿ⁺¹ _k = c ⁿ _k −α _ek , −MkN ...(3) Here, c ⁿ _k , c ⁿ⁺¹ _k is the nth field (n+1)
It means the value of c _k after field correction. In the (n+1)th field, {c ⁿ _k } is the formula
It is corrected according to (3) to become {c ⁿ⁺¹ _k } and stored in the tap gain memory 8 again.

The modified tap gain {c _k } is transferred to the tap gain holding circuit 10 via the switch 9 at the beginning of the next field, and is held at a constant value for one field.

By repeating the above operation for each field (every time a vertical synchronization waveform arrives), the value of {c _k } is automatically corrected in the direction that e(t) in equation (2) gradually becomes smaller.

If the control expressed by equation (3) converges stably, {c _k }
converges to a constant value, so all {e _k } inevitably become 0. For this reason, the tap gain modification control expressed by equation (3) is called the "zero-facing algorithm."

The biggest problem with this zero-facing algorithm is control convergence. This will be explained using a mathematical formula.

Substituting equation (1) and equation (2) into equation (3), the following equation is obtained.

c ⁿ⁺¹ _k = c ⁿ _k −α{x _k + _N 〓 ^i=M c ⁿ _i x _k-1 −r _k }, −MkN ……(4) Performing Fourier transform on both sides of the above equation, Rewriting it into frequency domain expression, C ⁿ⁺¹ (jω) = C ⁿ (jω) − α{C ⁿ (jω)X(jω) +
X(jω)−R(jω)}...(5) Here, C(jω), X(jω), and R(jω) are the Fourier transforms of the time series {c _k }, {x _k }, and {r _k }, respectively, and for example, C(jω)= _∞ 〓 ^{k=- ∞} c _k ε ^-jk 〓 ^T ……(6).

Equation (5) is transformed as follows.

C ⁿ⁺¹ (jω)={1−αX(jω)}C ⁿ (jω)−α{x
(jω)-R(jω)}...(7) The necessary and sufficient condition for this recurrence formula to converge is |1-αX(jω)|<1...(8).

Here, the shape of the voltage spectrum X(jω) of the input waveform will be considered. Since the input waveform {x _k } is a differential waveform of the vertical synchronization waveform, it has a shape approximately as shown in FIG. 2a near t=0. The real part of X(jω) obtained by Fourier transforming this has a form as shown in Figure 2b. Since the sampling frequency 1/T is originally set higher than twice the highest frequency of the input signal, X(jω) is 0 near ω=π/T. If X(jω) is in a non-zero frequency range and its phase falls within the range of -π/2 to π/2, the formula
Although (8) is satisfied, there is no guarantee that the phase of X(jω) is the same. Depending on the characteristics of the transmitting and receiving filters and the state of nearby ghosts, a frequency region where Re{X(jω}<0) may appear as shown in Fig. 2b. In such a case, the tap gain sequence {c _k } is Positive, negative, positive and negative to emphasize high frequency components...
While taking this repeating pattern, its absolute value gradually grows and diverges.

Traditionally, "leak integration" has been used as a method to avoid such problems with zero-facing algorithms.
A control method called . In this method, instead of the control according to equation (4), c ⁿ _k is leaked by a very small amount β c ⁿ _k during one field as shown in the following equation, and then the following equation is corrected.

c ⁿ⁺¹ _k = (1-β)c ⁿ _k −α{x _k + _N 〓 ^i=-M (1-β)c ⁿ _i x _k-1 −r _k }, −MkN ……(9) The necessary and sufficient condition for the control in equation (9) to converge is (1-β) | 1-αX (jω) | < 1 (β0)... (10), so as long as the above equation is satisfied If β is chosen large, the system will stably converge even if Re{x(jω)} has a negative region.

By introducing leakage integration, stable tap gain correction control is possible even with a zero-focusing algorithm, but the conventional leakage integration method has the following defects.

The leakage integration method is suitable for a system in which a portion corresponding to the tap gain memory 8 in FIG. 1 is realized by an analog memory having a time constant such as a capacitor memory. When analog memory is used, the tap gain memory 8 usually also serves as the tap gain holding circuit 10, and is arranged separately for each tap, and one adder circuit 7 is attached to the analog memory of each tap. do. In such a configuration, since there is a finite amount of leakage in the analog memory itself, the leakage integral control of equation (9) is inevitably performed.

On the other hand, from the viewpoint of ease of integration into an IC and retention of the tap gain value during abnormal operation, it may be desirable to implement the tap gain memory as a digital memory. FIG. 1 is an example of such a configuration.

However, when trying to apply the leakage integration method to an automatic equalizer using a digital tap gain memory, the following problems conventionally occur. Now assume that the number of bits in one word of the tap gain memory 8 is l bits including the sign. Further, the upper and lower limits of the tap gain value are set to ±1. At this time, the quantization level Δ of the tap gain value in the tap gain memory 8 is Δ=2 ^-(l-1) . . . (11).

Assuming that the tap gain value of a certain tap before leakage occurs is c _k and a leakage coefficient of β is added to this, the magnitude of the leak is βc _k . If we cut off the (l+1)th bit and below of the result of the digital operation β×c _k and limit the word length to l bits, we get a leak of the size |βc _k |<Δ=2 ^-l+1 ...(12) are all calculated as 0. For example, if l=12, β=2 ^-9 ≒0.002, |
For a tap gain of c _k |<2 ^-2 = 0.25, the leakage is zero.

In this way, while |c _k | is small, the leakage is 0, so {c _k } does not converge to the optimal value, and even the taps that do not directly contribute to ghost elimination take a uniform positive/negative positive/negative pattern. It grows to about ｜c _k ｜0.25. If the system reaches equilibrium in this state, the following disadvantages will occur, although this cannot be said to be a divergence.

First, the signal-to-noise ratio at the output of the tapped delay line filter is significantly reduced. The reason for this is that the noise power at the output stage of the tapped delay line filter increases approximately in proportion to the sum of absolute values of the tap gains.

Second, the connection method of the tapped delay line filter in the automatic equalizer is different from that shown in Fig. 1, and the rear taps (c ₁ to c _N ) is a cyclic connection. Such a cyclic tapped delay line filter is stable if the sum of absolute values of the tap gains is less than 1, but if it exceeds 1, the filter itself may become unstable. Therefore, if all the taps have a large value and the number of taps is several dozen or more, as in the above example, it will easily become unstable.

Next, unlike the above case, the digital operation β
Let us consider a case in which, among the results of xc _k , all bits below the (l+1)th bit are rounded up and 1 is added to the lth bit. In this case, |βc _k |
No matter how small is, the magnitude of the leak is always equal to or exceeds Δ. Assuming that the proportionality constant α for tap gain correction in equation (3) is α = 0.1, and the digital operation α×e _k is also rounded up from the (l+1)th bit onwards, the tap gain when |e _k | is smaller than 10Δ is The gain correction amount is Δ. This is equal to the minimum leakage value mentioned above. In other words, the amount of tap gain leakage and the amount of correction are just balanced, and the tap gain does not grow forever for an error (ghost) smaller than 10Δ. In this case, the operation of the system is extremely stable, but
This results in an insufficient effect for the original purpose of automatic equalization (ghost elimination).

It has thus far been considered difficult to apply leakage integral control to an automatic equalizer having a digital tap gain memory.

The present invention has been made in view of the above points, and
The present invention provides a stable automatic equalizer that makes it possible to apply leak integral control while using a digital tap gain memory.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 4 shows the overall configuration of an embodiment of the present invention, most of which is the same as FIG. 1. Therefore, in FIG. 4, parts common to those in FIG. 1 are indicated by the same numbers, and detailed explanation thereof will be omitted. The newly added parts in FIG. 4 are the coefficient circuit 12, addition circuit 13, addition circuit 14, constant leak generation circuit 15, and switch 1.
6, and a control circuit 17.

Tap gain value read out from tap gain memory 8 once per field for tap gain correction
_The coefficient circuit 12 inputs -β (0β
<1). In the multiplication result here, fractions below the (l+1)th bit are rounded down in the direction of decreasing the absolute value.
In the adder circuit 13, the calculation c _k −βc _k is performed,
A leak proportional to the value of c _k is given to c _k . However, as described above, when the value of |βc _k | is less than Δ, the leakage is 0. The tap gain value sized to (1-β) _ck is then passed to the adder circuit 14.
-Δsgn c _k from the constant leak generation circuit 15 is added. sgn c _k represents the sign of c _k . However, this addition of -Δsgn c _k is not performed for every field, but is performed only when the switch 16 is closed via the switch 16 as a selection means that is opened and closed by the control circuit 17. In other cases, −Δsgn c _k is not added and 0 is added. That is, the amount of effective leakage provided by adder circuit 14 is proportional to the length of time that switch 16 is closed. Therefore, by appropriately selecting the output waveform of the control circuit 17, it is possible to provide an arbitrary amount of leakage.

There are several methods for setting the operation of the control circuit 17. The first and simplest method is to close the switch 16 intermittently.
For example, the output waveform of the control circuit 17 is set to be "1" during only one field among a plurality of fields, and "0" during the other fields. FIG. 5 shows a specific example of the configuration.

In FIG. 5, a field start signal indicating the start of a field is sent from the timing circuit 11 in FIG. 4 to a binary counter 21, and the counter 21 counts this field start signal. Each digit output of the counter 21 is input to a decoder 22. The decoder 22 is set to output "1" every time the counter 21 counts a certain number of field start signals, for example eight.
In this way, the effective value of leak given by the adder circuit 14 can be considered to be approximately Δ/8, so
It is possible to provide an appropriate amount of leakage that is sufficient to suppress divergence even for tap gain values in a relatively small region, and that hardly impairs equalization performance (ghost cancellation performance). .

As another configuration example of the control circuit 17, although not particularly shown, instead of using the field start signal from the timing circuit 11 as an input to the counter 21 in FIG. 5, the output of a simple free-running oscillator may be used. Even at this time, the amount of leak provided by the adder circuit 14 can be arbitrarily set by the frequency division ratio L determined by the counter 21 and the decoder 22. However, if the oscillation frequency of the free-running oscillator becomes an integer multiple of the field frequency, there is a risk that a situation may occur where one tap is always given leakage and another tap is always not given leakage. , care must be taken when selecting the frequency.

Yet another method of configuring the control circuit 17 is to close the switch 16 only when a plurality of successive tap gain patterns centering around the tap gain c _k to be corrected is a predetermined pattern. An example of the configuration of the control circuit 17 is shown in FIG. In this example, the control circuit 17 includes a buffer memory 23, EXOR circuits 24 and 25, and an AND circuit 2.
Consists of 6. The buffer memory 23 temporarily stores only the sign of the tap gain value read out from the tap gain memory 8. Assuming that the tap gain c ⁿ _k of the k-th tap is now at a timing when it should be corrected, the buffer memory 2
sgn c ⁿ _k+1 read from the memory cell one place to the right of the left end of the tap gain memory 8 is sent to the tap gain memory 3. The number of stages of the buffer memory 23 is assumed to be two. At this time, the contents of the buffer memory 23 are sgn c ⁿ _k-1 on the right, sgn c ⁿ _k on the left, and sgn c ⁿ _k+1 in the input. In the EXOR circuit 24, sgn c ⁿ _k-1 and sgn
Take EXOR of c ⁿ _k , and if both have the same sign, “0”
If they have different signs, "1" is output. EXOR
Similarly, the circuit 25 outputs "1" only when sgn c ⁿ _k and sgn c ⁿ _k+1 have different signs. AND circuit 26
outputs "1" only when the outputs of the two EXOR circuits 24 and 25 are both "1". This is the final output of control circuit 17. That is, the output of the control circuit 17 becomes "1" (that is, c ⁿ _k -
Δsgn c ⁿ _k ) is given by {c ⁿ _k-1 ,
The tap gain series c ⁿ _k , c ⁿ _k+1 } is {positive, negative,
Positive} or {negative, positive, negative} pattern.

In the conventional automatic equalizer shown in Fig. 1,
It was mentioned earlier that the tap gain grows so as to emphasize the vicinity of the frequency 1/2T, that is, the positive/negative positive/negative...repetitive pattern grows. Therefore, by using the control circuit 17 having the configuration shown in FIG. 6, leakage can be applied to c _k only when a tap gain pattern of {positive, negative, positive} or {negative, positive, negative} appears. If you do this, this kind of pattern will be suppressed very strongly. On the other hand, at this time, the original equalization performance (ghost elimination performance) is hardly affected. The reason for this is that the tap gain pattern that contributes to ghost cancellation itself is usually as shown in Figure 7a (in-phase ghost) or Figure 7b (quadrature-phase ghost), with two or more consecutive positive and negative taps. many, {positive, negative, positive}, also {negative, positive, negative}
This is because the probability of taking the pattern is small. In order to keep the influence on the ghost erasing performance to a smaller extent, instead of being based on the sign of three consecutive taps as described above, for example, a pattern of positive, negative, positive, negative, etc. exists over five or more consecutive taps. All you have to do is give a leak only when the problem occurs.

In the embodiment shown in FIG.
A configuration is shown in which a β leak circuit (coefficient circuit 12 and adder circuit 13) that provides a leak βc _k proportional to c _k is inserted between the tap gain memory 8 and the adder circuit 14, but this part is not covered in the main text. It is not an essential component of the invention. This is because even if the β leak circuit is not inserted (in other words, even if β=0), the adder circuit 14 and the control circuit 1 in FIG.
Since there is another leak providing circuit consisting of 7, etc., the tap gain control system can be stabilized simply by appropriately setting the effective leakage amount in this leak providing circuit.

In addition, in the embodiment shown in FIG. 4, control is used such that the tap gain correction amount is proportional to the error e _k as shown in equation (3), but this is just one example. The gain correction amount is a constant value αΔ,
There may be a method in which only the polarity depends on the sign of e _k . This can be expressed as a formula: c ⁿ⁺¹ _k = c ⁿ _k −γΔsgn c _k −αΔsgn e _k ...(13) γ=1 or 0 (depending on the output of the control circuit 17)
becomes. At this time, the tap gain correction amount is a constant value, so a β leak circuit cannot be provided. β
This is because if a leakage circuit is installed, c _k cannot be larger than αΔ/β.

Furthermore, in the embodiment shown in FIG. 4, control such that the tap gain correction amount is proportional to the error e _k , that is, a zero-facing algorithm was used, but the present invention employs a control method other than this. Similar effects can be obtained when applied to an automatic equalizer. For example, the control expressed as c ⁿ⁺¹ _k = c ⁿ _k −α _∞ 〓 ^i=-∞ x _i e _i+k ...(14) is LMSE (Least Mean Square
Error) algorithm. In LMSE control, the equation corresponding to equation (7) is C ⁿ⁺¹ (jω)={1−α|X(jω)| ² }C ⁿ (jω)−
αX(−jω) {X(jω)−R(jω)} (15) Therefore, the value inside { } never exceeds 1, and the control is always stable. However, even in this case |
Since (jω)| remains almost 0 in the vicinity of the frequency 1/2T, the tap gain pattern of positive, negative, positive, negative, etc. will grow to a certain size if it continues as it is. As mentioned above, the growth of such a pattern is undesirable from the viewpoints of (1) an increase in output noise, and (2) stability when a cyclic configuration is used. Even when the present invention is applied to the LMSE algorithm, the same effect as the zero-facing algorithm can be obtained in suppressing this positive/negative/positive/negative pattern.

The embodiment shown in FIG. 4 is an example in which the present invention is applied to the automatic equalizer with the acyclic structure shown in FIG. 1, but the present invention can also be applied to the automatic equalizer with the cyclic structure shown in FIG. Of course, it is also possible to apply the invention. At this time, the main effect of the present invention, which is the suppression of positive/negative/positive/negative tap gain, is fully utilized.

In the explanation so far, the absolute amount of leakage generated in the constant leakage generation circuit 15 of FIG. It is obvious that Δ may be an integral multiple of Δ. That is, the leak generated by the constant leak generating circuit 15 is generally expressed as -KΔsgn c _k (where K is a positive integer).

As explained in detail above, according to the present invention,
In an automatic equalizer using digital tap gain memory, it is possible to add a desired constant amount of leakage to the tap gain regardless of the magnitude of the tap gain value, and as a result, the It is possible to prevent divergence in the tap gain correction control system, and in both the zero-facing algorithm and the LMSE algorithm, harmful positive, negative, positive and negative tap gains that do not directly contribute to automatic equalization without impairing equalization performance can be used. Pattern growth can be effectively suppressed.

[Brief explanation of drawings]

Figure 1 shows the configuration of a conventional automatic equalizer, Figure 2 shows the time waveform of the input signal to the automatic equalizer and its frequency spectrum, and Figure 3 shows the configuration of a conventional automatic equalizer. FIG. 4 is a diagram showing a configuration of an automatic equalizer according to an embodiment of the present invention, FIG. 5 is a diagram showing a configuration of a control circuit according to the present invention, and FIG. 6 is a diagram showing a configuration of an automatic equalizer according to an embodiment of the present invention. FIG. 7 is a diagram showing another example of the circuit configuration, and is a diagram showing a typical example of a tap gain pattern that directly contributes to ghost cancellation. 1...Delay line filter with tap, 8...Tap gain memory, 14...Addition circuit, 15...Constant leak generation circuit, 16...Switch (selection means), 1
7...Control circuit.

Claims (1)

[Scope of Claims] 1. A tapped delay line filter with variable tap gain to which a signal to be equalized is input; a digital tap gain memory that stores a tap gain value to be given to the tapped delay line filter; tap gain modifying means for modifying the tap gain value successively output from the tap gain memory in a direction that minimizes distortion of the output signal of the delay line filter with taps and re-inputting the modified tap gain value to the tap gain memory. In the automatic equalizer, adding means is provided in a path from which the tap gain read from the tap gain memory is re-inputted to the tap gain memory via the tap gain modifying means, and one of the adding means is provided. −KΔsgn c _k (sgn c _k is the tap gain to be corrected
c (sign of _k , K is a positive integer, Δ is the quantization level of the tap gain in the digital tap gain memory), or selection means for selectively giving a value of 0; In order to prevent excessive growth of tap gain, -
An automatic equalizer comprising a control means for selecting KΔsgn c _k and selecting 0 for other periods. 2. The control means consists of a binary counter and a decoder, and divides the constant frequency input signal to the binary counter by L (L is an integer) to obtain the output signal of the duty factor 1/L, and this output signal is 2. The automatic equalizer according to claim 1, wherein the selection means is made to select -KΔsgn c _k only when the value is "1". 3. A tapped delay line filter with a variable tap gain into which the signal to be equalized is input; a digital tap gain memory that stores the tap gain value to be given to this tapped delay line filter; an automatic equalizer comprising tap gain modifying means for modifying the output tap gain value in a direction that minimizes distortion of the output signal of the tapped delay line filter and re-inputting the modified tap gain value into the tap gain memory, Adding means is provided in the path until the tap gain read from the tap gain memory is re-inputted to the tap gain memory via the tap gain modifying means, and -KΔsgn c is provided as one input of the adding means. _k (sgn c _k is the tap gain to be corrected
c (sign of _k , K is a positive integer, Δ is the quantization level of the tap gain in the digital tap gain memory), or selection means for selectively giving a value of 0; In order to prevent excessive growth of the tap gain of , only when a plurality of consecutive tap gain patterns centering on the tap gain c _k to be corrected is a predetermined pattern -
An automatic equalizer comprising a control means for selecting KΔsgn c _k and selecting 0 for other periods. 4. The control means applies -KΔsgn c _k to the selection means only when the signs of three or more consecutive tap gains centered on the tap gain c _k to be corrected are all opposite signs. 4. The automatic equalizer according to claim 3, wherein the automatic equalizer allows selection.