JPS6370176A - Ic circuit - Google Patents

Abstract

PURPOSE:To simplify the test of a specified circuit block alone, by connecting an input condition register to a front stage of the specified circuit block and an output condition register to a rear stage thereof respectively. CONSTITUTION:During a normal operation, with the supply of a high level signal to a through signal input terminal 12 from outside, signals from circuit blocks are fed to other circuit blocks passing through condition registers 10 and 11. On the other hand, with the supply of a low level signal to a through signal input terminal 12 from outside, both the condition registers 10 and 11 operate as shift register. In other words, a test signal to be fed to a test signal input terminal 10a is supplied sequentially to signal input sections I1-In of a circuit block 2. Output signals of signal output sections O1-On are supplied to the output condition register 11 and outputted from a test signal output terminal 11a sequentially.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC circuit suitable for an IC circuit constructed with a small number of circuit blocks.

[Summary of the invention]

The present invention provides an IC circuit suitable for an IC circuit configured with a plurality of circuit blocks.
A manually operated conditioning register that can select between the input signal through state and the operating state as a shift register is connected to the subsequent stage of a predetermined circuit block, allowing the input signal through state and the operating state as a shift register to be selected. By connecting an output condition register, it is possible to easily test only this predetermined circuit block.

[Conventional technology]

Conventionally, as an IC circuit with a relatively large circuit configuration, the second
There was something like the one shown in the figure. In this Figure 2, (1
) indicates the entire IC circuit, and this IC circuit (1) includes multiple circuit blocks (2), (3), (4),
(5), (6), (7).

(8) . . . is provided when a predetermined connection is made.

For example, circuit blocks (3), (4),
(5) has terminals (3m), (3b), (3c), and (4m) as signal input terminals from the outside of the IC circuit (1), respectively.
, (4b), (4c), (5m) and (5b),
These respective circuit blocks (3), (4) and (5)
A predetermined output signal of is supplied to the circuit block (2).

Further, a predetermined output signal of this circuit block (2) is supplied to circuit blocks (6), (7) and (8).

Furthermore, this circuit block C6), (7) and (8)
) have terminals (6m), (6b) = (6e), (7a), (
7b), (7e), (8a) and (8b). Further, although not shown, the IC circuit [1] is provided with circuit blocks other than those described above, and the respective circuit blocks are arranged with predetermined connections.

By configuring the inside of the IC circuit (1) with a plurality of blocks in this manner, design etc. can be simplified. For example, by designing each circuit block by a different designer, efficient design can be achieved.

[Problem that the invention seeks to solve]

However, since each circuit block of the above-mentioned IC circuit (1) is integrated internally, there is a problem in that it is not possible to test the operation of each individual circuit block alone. Department,
When testing the operation of this IC circuit (1), a test signal is supplied from the input terminals (3m), (3b), etc., and passes through each circuit block to the output terminals (6a), (
6b)..., but in such operation tests, even if an abnormality occurred in the output signal, it was not easy to determine which circuit block was the cause. For this reason, we prepared a variety of complex signals as test signals and connected them to the output terminals (6m) and (6b).
It is necessary to be able to tell the status of each circuit block only from the signals obtained from ..., which is disadvantageous in that it takes time and effort to develop test signals and also requires a long test time.

SUMMARY OF THE INVENTION In view of these points, it is an object of the present invention to provide an IC circuit that allows testing of only a predetermined internal circuit block.

[Means for solving problems]

In the IC circuit of the present invention, as shown in FIG. 1, for example, an input condition register (IC) is connected at the front stage of a predetermined circuit block (2), which allows selection of an input signal through state and an operating state as a shift register. However, an output condition register α21 is connected to the subsequent stage of this predetermined circuit block, allowing selection of an input signal through state and an operating state as a 77 register.

[Effect]

The IC circuit of the present invention has an input condition register (1
0 and the output condition/run register Ql) are set to pass input signals during normal operation, and operate as a shift register during testing.
Input condition register α which became a shift register
By supplying a test signal to Q, this test signal can be taken out from the output condition register α°C via a predetermined circuit block (2), and the predetermined circuit block (2)
You can easily test just that.

〔Example〕

An embodiment of an IC circuit according to the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

The IC circuit of this example is constructed as shown in FIG.

In this FIG. 1, (9) shows the entire IC circuit, and this IC circuit (9) includes a plurality of circuit blocks (2), (3), (4), (5) as in the example in FIG. )
# (6), (,7), (8)... are arranged, and in this example, the circuit block (2) can be tested. That is, circuit block (2) has 11.1 as a signal input section from other circuit blocks. There are I2゜engineering5...l1ll (n is an integer), and O,,02,O,...O,(
Assuming that there is an integer), other circuit blocks and this signal input section I + ~ engineering. An input condition register q0 is connected between the signal output units O4 to On and other circuit blocks, and an output condition register αη is connected between the signal output units O4 to On and other circuit blocks. This input condition register QQ is -IC
The circuit (9) is provided with a test signal input terminal (10) and a shift register operating signal input terminal (10b) as terminals to which signals are supplied from outside, and the test signal is transferred to the shift register depending on the supply state of the through signal, which will be described later. It is sequentially supplied to each input section of the circuit block (2) in synchronization with the actuation signal. The output condition register C1υ also includes a test signal output terminal (11&) as a terminal for outputting a signal to the outside of the IC circuit (9), and a terminal for operating a shift register as a terminal to which a signal is supplied from the outside of the IC circuit (9). The output terminal (lla) is provided with a signal input terminal (llb), and output signals from each output section of the circuit block (2) are synchronized with the shift register operation signal depending on the supply state of a through signal, which will be described later.
Output sequentially from

(-), a through signal is supplied to both condition registers α0.αυ from the outside of the IC circuit (9) via the input terminal (6), and both condition registers α0. , αη and circuit block (2) are ICs.
A clock signal is supplied from outside the circuit (9) via the input terminal (to).

The IC circuit (9) is configured as described above, and during normal operation, the through signal input terminal (6) is connected to the through signal input terminal (6) from the outside, for example.
By supplying the level signal, the signals from each circuit block are transmitted to both condensation registers σ0. The signal is supplied to other circuit blocks in a through state within Qυ. That is, circuit blocks (3) and (4).

From (5) etc., each input part work 1 to work of circuit block (2).

Supply of signals to and each output section 01 of circuit block (2)
~On to circuit blocks (6), (7), (8
), etc., so that the input and output condition registers a* and U have no effect on the supply of signals. In this state, the IC circuit (9) of this example functions as a circuit similar to a conventional IC circuit.Then, the IC circuit (9) of this example supplies, for example, a low level signal to the through signal input terminal (6) from the outside. Therefore, both condition registers (, Ll, αυ,
It now operates as a τ shift register. In this manner, the circuit block (2) is tested by supplying test signals while operating as a shift register. That is, the test signal supplied to the test signal input terminal (loa) of the input condition register α1 is sequentially/shifted in synchronization with the signal obtained from the shift register operating signal input terminal (10b), and the test signal of the circuit block (2) is shifted. Each signal input section 11~. This footed signal is sequentially supplied to. Then, the output signals to each signal output section O1 of the circuit block (2), which are output according to the signals of each input section ~In, are supplied to the output condition register α9. ]) In order to operate as a mo shift register, each signal output section O1
~On output signals are sequentially shifted in synchronization with the signal obtained from the shift register operating signal input terminal (llb),
From the test signal output terminal (lla) to each signal output section 01~
All ON output signals are sequentially output.

The test signal supplied to the test signal input terminal (tOa) of the input condition register αO in this way is passed through each information input/output section in the circuit block (2) to the test l1g of the output condition register (11). By being output from the signal output terminal (lla), the test signal passes only through the circuit block (2) in the IC circuit (9), and the state of the signal obtained at this output terminal (l1m) is By monitoring, only the circuit block (2) can be checked.

In this way, according to the IC circuit (9) of this example, by changing the state of the through signal supplied to the through input terminal (6) and using the input/output condition register Qo eαυ as a shift register, it is possible to directly communicate the signal with the outside. Only circuit blocks (2) that do not have input/output terminals can be checked. Therefore, the test signal only needs to be a signal for checking one set of circuit blocks (2), so it can be a short and simple signal, which can shorten the checking time and save time and effort in developing the test signal.

In the above embodiment, input and output condition registers OQ are provided before and after the set of circuit blocks (2).

Although only the case in which (b) is provided has been described, registers <10 and CLη may be similarly arranged in other circuit blocks to facilitate testing. moreover,
It goes without saying that the present invention is not limited to the above-described embodiments, and that many other configurations can be adopted without departing from the gist of the present invention.

〔Effect of the invention〕

According to the IC circuit of the present invention, a predetermined circuit block (2)
By connecting the input condition register αO and the output condition register αυ to the front and rear stages of the circuit block (2), it is possible to easily test only this circuit block (2), shortening the test time and simplifying the test signal. There is profit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an IC circuit according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional IC circuit. (2) , (3) # (4) l (5) , (
6), (7), (8) are circuit blocks, (9)
is the IC circuit, αO is the input condition register, αη
is the output condition register.

Claims (1)

[Claims] An input condition register that can select the through state of the input signal and the operation state as a shift register is connected to the front stage of a predetermined circuit block, and the input condition register that can select the through state of the input signal and the operating state as a shift register is connected to the stage after the above predetermined circuit block. 1. An IC circuit characterized in that an output condition register is connected to which an output condition register can be selected.