JPS6372146A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to semiconductor integrated circuit technology and to technology that is particularly effective when applied to electrostatic damage prevention measures in semiconductor devices. This article relates to techniques that are effective for use in protection circuits.

[Prior Art] Conventionally, as a measure to prevent electrostatic damage in a bipolar semiconductor integrated circuit, an input protection circuit as shown in FIG. 4, for example, is provided for an input pin. In this circuit, when a high voltage higher than a specified input voltage is applied to the input terminal 1, the diode d1 is turned on and a current flows toward the power supply voltage Vcc. In addition, when a low voltage below the specified input voltage is applied to input terminal 1, diode d2
is turned on and current flows toward power supply voltage VEE. This prevents the elements constituting the input circuit from being destroyed. The above-mentioned input protection circuit is described, for example, in Japanese Patent Application No. 4911/1983.

[Problems to be Solved by the Invention] However, in conventional bipolar integrated circuit devices, a protection circuit for preventing electrostatic damage is provided only for the input bin, and no electrostatic damage countermeasures are taken for the output pin. Ta. This is because the output circuit of a bipolar integrated circuit is composed of fairly large transistors that can drive a large load, such as 50Ω, so it was thought that there was no need to take measures against electrostatic damage.

However, upon detailed study by the present inventor, when a negative voltage is applied to the output bin of a bipolar integrated circuit, current is drawn from the emitter terminal of the output transistor, so there is no particular problem. +100
It has been found that when a voltage with a positive polarity such as 0V is applied to the output pin, the withstand voltage between the emitter and collector of the output transistor may be exceeded, and the junction of the output transistor may be destroyed.

Particularly in recent years, in bipolar integrated circuit devices, base regions and emitter regions have become shallower (shallower diffusion), which has lowered the withstand voltage of output transistors, making them more susceptible to electrostatic discharge damage.

An object of the present invention is to provide a semiconductor integrated circuit technology that can effectively prevent electrostatic damage to output transistors in a bipolar integrated circuit.

Furthermore, another object of the present invention is to provide a master slice LSI.
An object of the present invention is to provide a semiconductor integrated circuit technology that can effectively prevent electrostatic damage of output transistors without adding any new elements or processes.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, in a bipolar integrated circuit, a protection diode is connected between the emitter terminal of the output transistor and the positive power supply voltage terminal of the circuit so as to be in the forward direction toward the power supply voltage terminal.

In addition, in a master slice LSI, a diode provided to protect the input transistor is connected between the emitter terminal of the output transistor and the positive power supply voltage terminal of the circuit so that the diode is in the forward direction toward the power supply voltage terminal. It is intended to do so.

[Operation] According to the above means, even if a positive abnormal voltage is applied to the output pin, current flows toward the power supply voltage terminal of the circuit through the protection diode connected to the output pin, and the output transistor is Reverse current will no longer flow. Also,
In a master slice LSI, an input circuit and an output circuit are prepared in advance for each bin, and when used as an output pin, not only the corresponding input circuit but also its input protection diode remains unused, so it is used for output protection. By using it as a diode, the above object of preventing electrostatic damage to the output transistor can be achieved without adding any new elements.

[Embodiment Figure 1 shows the present invention in an ECL (emitter coupled
LSI (Logic) circuits formed by the master slicing method such as gate arrays that use logic circuits as basic gate circuits.
An example in which the present invention is applied to a master slice LSI (hereinafter referred to as a master slice LSI) is shown.

In the master slice LSI, as shown in FIG. 1(A), an element group constituting the output circuit 2 and an element group constituting the input circuit 3 correspond to each of the input/output terminals 1 provided on the chip. It is provided. Furthermore, when a protection circuit as shown in FIG. 4 is connected to the input circuit 3, diodes d1 and d2 constituting the protection circuit are also provided for each input/output terminal 1.

In this embodiment, the diode d2, which was conventionally provided only to constitute an input protection circuit, is also used as a protection diode for preventing electrostatic damage of the output transistor. In other words, 1. For example, when the input/output terminal 1 of interest is used as an input bin and the input circuit 3 is connected to that bin when wiring is formed by the master slicing method, the input/output terminal 1 of interest is used as an input bin and the input circuit 3 is connected to the bin when forming wiring by the master slicing method. Connect these points with aluminum wiring. Then, a protection circuit as shown in FIG. 4 is constructed.

On the other hand, when connecting the output circuit 2 instead of the input circuit 3 to the input/output terminal 1 of interest and using it as an output pin,
In Fig. 1(B), the points shown by the dashed lines b, b2 and b3 are connected using aluminum wiring. Then, the third
As shown in the figure, a diode d2 is connected between the emitter terminal of the ECL type output output circuit 2 mitter follower transistor (output transistor) Qe connected to the output terminal 1' and the power supply voltage terminal Vcc such as a ground point. is connected in a forward direction toward the ground point.

Therefore, when an abnormal positive voltage that exceeds the emitter-collector breakdown voltage of the transistor Qe is applied to the output terminal 1'' from the outside, a bypass current flows toward the ground through the diode d2.As a result, Breakdown of the emitter-collector junction of the output transistor Qe is prevented.

In the embodiment shown in FIG. 1, the case where d2 of the diodes d□ and d2 prepared for the input protection circuit is used as the protection diode of the output transistor Qe has been described, but the diode d is used instead of the diode d2. Do you, d
, and di may be used by connecting them in parallel.
By using both diodes d1 and d2, the electrostatic breakdown strength of the output pin can be further improved compared to the case where only one diode is used.

Note that the diode d1 in the above embodiment is as follows.

It is formed using a base-collector PN junction of an element having the same structure as the transistors constituting the output circuit 2 and the input circuit 3. In addition, the diode d2 is connected to a P-type semiconductor region 11 which becomes the base region of the transistor as shown in FIG.
Use it as a resistor for input protection.

Further, it is formed using a PN junction between this P type semiconductor region 11 and N+ type buried layer 12. In Figure 2, 1
3 is an N-type epitaxial layer, 14 is an N+-type semiconductor region which becomes a collector pull-up port in the transistor, and 15a
-15c are aluminum electrodes.

Note that although the above embodiment has been described as applied to a master slice LSI, the present invention is not limited thereto;
It can be applied to output circuits of bipolar integrated circuits in general.

As explained above, in the present invention, in a bipolar integrated circuit, a protection diode is connected between the emitter terminal of the output transistor and the positive power supply voltage terminal of the circuit in a forward direction toward the power supply voltage terminal.
Even if a positive abnormal voltage is applied to the output pin, the current flows through the protection diode connected to the output pin toward the power supply voltage terminal of the circuit, and no reverse current flows to the output transistor. Electrostatic damage to transistors can be prevented.

In addition, in the master slice LSI, the diode provided to protect the input transistor is connected between the emitter terminal of the output transistor and the positive power supply voltage terminal of the circuit so that the diode is in the forward direction toward the power supply voltage terminal. This has the effect that electrostatic damage to the output transistor can be prevented without adding any new elements.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, it has been explained that the protection diode for preventing electrostatic discharge damage has substantially the same structure as other transistors, but the protection diode and the transistor may have completely different structures.

In the above explanation, the invention made by the present inventor was mainly applied to the field of application which is the background of the invention, which is to prevent electrostatic damage of output pins in bipolar integrated circuits, but the invention is not limited thereto. It can also be used in MO8 integrated circuits.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to effectively prevent electrostatic damage of the output transistor in the semiconductor integrated circuit.

[Brief explanation of the drawing]

FIGS. 1(A) and (B) are explanatory diagrams showing an example of the configuration of an input/output circuit of a master slice LSI to which the present invention is applied and its connection method. FIG. 2 is an example of the structure of a protection diode. 3 is a circuit diagram showing a state in which a protection diode is connected to an output pin. FIG. 4 is a circuit diagram showing an example of an input protection circuit in a conventional bipolar integrated circuit. 1... Input/output terminal (bin), 2... Output circuit,
3...Input circuit, d,, d2...Protection diode, Qa...Output transistor. Figure 1 (B) Figure 2 Figure 3

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device in which an output circuit is constituted by a bipolar transistor, a protective diode is provided between an output terminal to which the bipolar transistor is connected and a power supply voltage terminal of the circuit. A semiconductor integrated circuit device characterized in that it is connected. 2. An element for configuring an input circuit and an element for configuring an output circuit are provided for each given input/output terminal, and a desired logic circuit is configured using the wiring format using the master slicing method. In the semiconductor integrated circuit device, a common protection diode is provided for the input circuit and the output circuit, and the protection diode is selectively connected to either the input circuit or the output circuit. A semiconductor integrated circuit device according to claim 1, characterized in that: