JPS6373295A - Image display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to an image display device using a liquid crystal matrix panel sound.

(b) Prior Art FIG. 6 is a diagram showing a liquid crystal display device employing an active matrix liquid crystal spring /I/ used in a liquid crystal TV device. Are listed.

In the same figure, an active-manufactured liquid crystal spring/
L/(1) pixel t'' in n columns in the ) are connected in a matrix as shown in the figure, each row (Gl, G2, . . . Gm) and each column (Dl, D2, .
...Dn) are the row driver (2) and column driver (2), respectively.
3) is connected to. The row driver is composed of an m-stage shift register (2a) and an output circuit (2b), and the column driver is composed of a 1-stage shift register (3a), a sample hold circuit (3b), and an output circuit (3C). Ru. (4) is a synchronization control circuit, which controls the first synchronization signal based on the horizontal synchronization signal (Hp) and vertical synchronization signal (Vp).
, second start pulse (STI) (Sr1) and filter 1,
Second clock pulse (CP 1 ) (CP 2 )'
? Created.

FIG. 7 is a diagram showing each waveform of the row driver, and the figure (a)
represents video No. 18, and vertical synchronization No. 1a (V
p) and the horizontal synchronous signal '+(Hp) are multiplied by M. In the figure, T1 is a vertical synchronization signal period, T2 is a vertical blanking period, and T
3 is the video (t'F section).

Shift register (2a) K has a first start pulse (STI) synchronized with the vertical synchronization signal and a first clock pulse (CPI) synchronized with the horizontal synchronization signal as shown in FIGS. 7(b) and (c).
is given, and each row Gl, G2... has (d) (e) (
As shown in f), a voltage waveform shifted by IH (one horizontal period) is applied. This voltage waveform turns on the TPT (la) of each row sequentially in the horizontal retrace interval to uniformly apply liquid crystal drive pressure to each pixel. Add 7.

On the other hand, the waveforms of each part of the column driver (3) are as shown in FIG. The column drive does not change the same operation in each IH section. FIG. 8(a) shows the drawing friend video signal with the entire IH section at 78 expanded. In the figure, 'r4 is a horizontal synchronizing signal interval and a horizontal retrace interval, and T5 is an interval in which video information is included.

The shift register (3a) receives a second start pulse (Sr1) synchronized with the horizontal synchronizing signal shown in FIG. 8(b) (cl).
A second tarlock pulse (CP2) with a frequency of period τ=T 5 /n is applied to the output of each stage of the shift L/register 3a) as shown in the figure (di(e)(f)). Pulses shifted by τ are sequentially output.Each stage of the sample and hold circuit (3b) is controlled by the output of the shift register of each corresponding stage, and the voltage value of the video signal is sampled by the fall of the output. It is held until the next sample (between IHO).The output circuit (3C) receives the output of the sample and hold circuit, buffers it, and UJs all the column electrodes. Since this is done by sequentially switching four transistors per stage using a clock, the delay time per transistor stage must be within the clock cycle in order to operate. Since a transistor with a high switching speed is required, a transistor with a slow switching speed such as the a-5iTFTL7) used in the liquid crystal panel il+ cannot be used.

For this reason, the applicant has proposed an image display device that can use transistors with relatively slow switching speeds as part of the drive circuit (Special Patent No. 6L-108).
969). As shown in Figure 4, the previously proposed image display device uses a shift register, counters (50) and (60) that count clock pulses and derive a binary count value and its inverted output, and all outputs of this counter. A decoder (51) (61) which decodes and generates pulses that are sequentially shifted in each row and column of the matrix spring 7v (11) in synchronization with the clock pulse; constitutes a delimiter circuit. .

(c) Interjection point to be solved by the invention In rice bag r+1, the decoders (51) and (61) have counters (50) and (60) as previously proposed.
), as shown in FIG. 5, not only the signal lines a and b of each bit but also their inverted signal a.

One hundred is entered. i.e. Karan Ri150) or (
60) is an N-bit counter, and even the decoder (5
A 2N tree is required as an input to 1), and these 2N signal lines are coupled to the gates of the transistors of the decoder (51). Therefore, there is a risk that the increase in the number of signal lines will complicate the structure of the decoder (51) circuit 2 and reduce the manufacturing yield.

B) Means for Solving the Problems The image display device of the present invention includes a counter that counts the clock pulses to derive a binary count value, and decodes the output of this counter to display each row and/or column,
A decoder that generates all the pulses that are sequentially shifted in synchronization with the clock pulse is arranged in parallel on an active matrix spring μ, and the decoder is composed of an n-channel thin film transistor and an n-channel thin film transistor that respond to the binary count value of the counter. According to the image display device of the present invention, the binary count value of the counter can be decoded by the p-channel and n-channel lv film transistors, and the inverted output of the binary count value is There is no need to use . Therefore, the total input line from the counter to the decoder circuit is halved.

(f) Embodiments FIGS. 1 and 2 show all different embodiments of the drive circuit of the image display device of the present invention. In FIG. 1, the first pin Fa/li of the binary count is the p-type T of the first and third rows of 8 wires.
F TIIIG Fox 2nd and 4th Yukinobu 8-wire n-type TF
T! The second bit b is connected to each gate of 21t'E,
1 type TFTGU +42 of 3rd and 4th row line '1+ line
The counter t/i2 is connected to each gate of
It has a 4-bit output configuration, and when the counter is 0, its outputs are a=ゝゝ0'', b=ゝゝ0''.

When the counter is 1, its output ft, a =ゝゝ1'', b
=″0/I.

When the counter is 2, its output is a;ゝゝ0//, b=
SS 111゜When the counter is 3, its output is a=1'
1"lb=ゝゞ1" When the truth value is set, in this decoder (51), the negative voltage No. 1 corresponding to 10" is p
The channel channel 1vTFT'kON is set, and a positive voltage No. 18 corresponding to 1" turns the n-channel/I/TPT OFF.

Therefore, now when the counter is 0, T F T (II) 021
Since 3η is ON and TPTall(2) (4υ(6) is OFF), the 4 outputs P1 from the decoder (51)
~p4, TPTtll in ON state) (Only the first output signal t1 on which one force acts becomes High. Therefore, n
Channel/vT F T (I4) (+5) (241t
25] In the output circuit (52) configured by f45iK (to C14), TPT (I4) is turned on, so
Among the 4 gate signals (Gl to G4), the gate signal G of il
Only 1 becomes High.

Next, counter viJ) increments from O to 1 and is 9, TPT state 21)■4D of decoder (51) is ON, TFT (
lsu3υ(a)←2 becomes OFF, and the output port 'ji'y
Only G2 is High1, so only gate signal G2 is High.
h.

In this way, according to the progress of the counter, the gate signal J
j+G1~G4 becomes eruption High, and liquid crystal spring /1/
It stores one.

Further, in the embodiment shown in FIG. 2, an Ffr different from the embodiment shown in FIG. 1 is located in the output circuit (52'). That is, the circuit (
52) ipp channel TT F T ;j41 starvation C3
111t44 and n-channel TFTt15) 251(to)ura are connected in a complementary manner, and either the HP channel TPT or the n-channel TFT 1vTFT is turned off except during switching, so current consumption is reduced. Small.

Figure 3 shows p-channel TPT and n-channel IvTF.
This shows the process of forming T and T on the same substrate, that is, an active matrix panel. As shown in FIG.
A conductive layer (100) made of ITO or gold, which will become the source and drain Jtf, is applied and patterned using a trisogera phyr to form a predetermined pattern. Next, the same figure (b)
Turning the amorphous silicon k of nq to the source and drain poles (200) (200) of the n-channel/L'TPT and turning the k pattern. On top of this, p-channel/L/TPT source and drain electrodes (300) (
Attach the p-type amorphous silicon (300) to the n-type amorphous silicon (200) (200): 6
Buttering is performed as shown in the same figure (cl) so that Ei remains.

Furthermore, as shown in Figure (d), the sabotage head relatives of both TPTs (
400) type 1 (intrinsic) amorphous silicon is then patterned. An insulating film of 5i02°Si8N4 or the like is attached on top of the black plate shown in FIG. Finally, as shown in FIG. 5(f), a conductive layer such as aluminum, which will become the gate 1!0f (600), is patterned.

In the above explanation, we will explain the drive circuit of the gate signal 8-line sword using the Kihatsu E! Although we have implemented method A, it goes without saying that it can be adopted for the drive circuit on the drain signal line side.

(G) Effects of the Invention According to the image display device of the present invention, the decoder can be connected to p-channel/'7j! Since it is configured with a combination circuit of a simulated transistor and an n-channel thin film transistor, the counter can be decoded using the binary count value without using its inverted output. Therefore, the input from the counter to the decoder circuit By reducing the number of wires by half, it is possible to simplify the decoder configuration and improve yield.

[Brief explanation of the drawing]

Figures 1 and 2 are circuit diagrams of embodiments of the image display device of the present invention with different drive parts, Figures 3 (a) to 3) are cross-sectional views of the manufacturing process of the device of the present invention, and Figure 4. 5 is a block diagram of the previously proposed device, FIG. 5 is a driving portion circuit diagram of the previously proposed device, FIG. 6 is a block diagram of a conventional device, and FIGS. 7 and 8 are signal waveform diagrams. (1)... Matrix spring le, (50) (60)... Counter, (51 bar 81)... Decoder, (5
2) (63)...Output circuit.

Claims (2)

[Claims] (1) In an image display device in which each row and each column of an active matrix panel in which a plurality of pixels are arranged in a matrix is selected by a clock pulse of a predetermined frequency to drive each pixel, the clock pulse is A counter that counts and derives a binary count value, and a decoder that decodes the output of this counter and generates pulses that are sequentially shifted in synchronization with the clock pulses in each row and/or each column are provided on the active matrix panel. 1. An image display device, characterized in that the decoder is comprised of a p-channel thin film transistor and an n-channel thin film transistor that respond to a binary count value of a counter. (2) The image display device according to claim 1, wherein the output circuit of the decoder is composed of a p-channel thin film transistor and an n-channel thin film transistor.