JPS637517B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a wireless remote control system using wireless carrier means, which has multiple channels, and allows remote control by individually selecting any receiver from a large number of receivers. The present invention relates to a multi-channel remote control system.

First, a conventional example of a multi-channel remote control system, which is the premise of the present invention, will be explained. In addition, in this conventional example, a large number of pairs of transmitters 1 and receivers 2 are provided in a one-to-one correspondence, and an address information signal for selecting the corresponding receiver 2 is sent from any one transmitter 1. The transmitter 1 is configured to transmit the data using a wireless carrier, and the receiver 2 that receives the data determines whether or not it matches its own address setting data and controls the load 3. It is also possible to make a plurality of receivers 2 correspond to each other, create an address information signal for each receiver 2 in the transmitter 1, and call and control each receiver 2 individually using a circuit similar to the conventional example below. It was realized by. The transmitter 1 generates two types of frequency signals, for example, frequencies _f1 and _f2 , as modulation signals, and allocates one frequency to each unit time having a unit switching period of Tw in time length. Create an address information signal, which allows for example 300MHz
The antenna 4 modulates a carrier wave signal of about 100 MHz and sends it out as a wireless signal from the antenna 4. As shown in FIG. 1, the address information signal has a frequency f ₁
It is formed as a time-series frequency signal that is formed by combining the signals of and f ₂ with one frequency for each unit time, and the example in Fig. 1 shows the case where this address information signal is composed of 6 units. . On the other hand, the receiver 2 includes a front end 5 composed of, for example, a super regenerative circuit including two transistors, and a gain of 80 _dB.
a gain amplifier 6 whose center frequency is set to f ₁ and f ₂ , bandpass filters 7 ₁ and 7 ₂ whose center frequencies are set to f 1 and f 2, respectively, and an address setting section 8 formed of something like a pin board. , and a discrimination circuit 9 formed of an arithmetic processing LSI such as a microcomputer and inputting the outputs of the filters 7 ₁ and 7 ₂ and the output of the address setting section 8, and the outputs of the filters 7 ₁ and 7 ₂ (actually This filter 7 ₁ , 7 ₂
The output is digitized by a comparator),
A shift register 10 that is read and temporarily stored in synchronization with a clock signal corresponding to the unit switching period Tw on the transmitter 1 side is built into this discrimination circuit 9, and the storage contents of this shift register 10 and the settings of the address setting section 8 are A comparison circuit 12 compares the content stored in the memory 11, which stores the content, to detect its own call. The discrimination circuit 9 that has detected the call in this way also discriminates the added control data as necessary, and drives the speaker as the load 3 to produce a chime sound, or activates a relay to control an appropriate external load. It is designed to drive and control a relay output circuit that has a relay output circuit. Therefore, the address information signal consisting of a modulated carrier signal received by the transmitting antenna 13 is amplified and demodulated by the front end 5, and is inputted in parallel to each filter 7 ₁ and 7 ₂ via a gain amplifier 6. The filters 7 ₁ , 7 ₂ correspond to two frequencies f ₁ , f _{2 ,} respectively, and produce an output from the filters 7 ₁ , 7 ₂ that matches the frequency of the demodulated signal received at that time,
The outputs of the corresponding filters 7 ₁ and 7 ₂ are digitized by a digitizing means such as a comparator, and outputs corresponding to the frequencies f ₁ and f ₂ of the address information signals as shown in FIG. 3a and b are generated. and is input to the discrimination circuit 9. The discrimination circuit 9 is _configured to perform the functional operation as _shown in _{FIG .} The input digital signals as shown in FIG. 3 a and b are read as data shown in FIG. 3 c and d, respectively, and address information as shown in FIG. 3 e is temporarily stored in the shift register 10. Become. Further, the address setting data set by the address setting section 8 is inputted to the discrimination circuit 9 by the address input circuit 15 and stored in the memory 11. Thus, in the discrimination circuit 9, the shift register 1
A comparison circuit 12 compares the received address information temporarily stored in the memory 11 with the address setting data stored in the memory 11, and when the two match, the output circuit 16 is activated to control the external load 3. It is.

As described above, when the discriminating circuit 9 transmits and processes the received address information signal, the filters 7 ₁ ,
7 ₂ is sampled and input to the discrimination circuit 9. Conventionally, the outputs corresponding to frequencies f ₁ and f ₂ from the filters 7 ₁ and 7 ₂ shown in FIG. Sampling was performed using a clock signal shown in FIG. 5B, and the data was read into the shift register 10 as address information shown in FIG. 5C. However, there is a drawback that the discriminating circuit 9 may make erroneous judgments due to delay elements such as inductance, noise, etc. that each circuit itself has. That is _, in a _{normal state} , as _shown in _{FIG .} , the address information is always "01 _" or "10" as shown in FIG. 5c, but as shown in _FIG . When noise N occurs, if the time at which the noise N occurs is exactly the same as the clock signal shown in Figure 6b, the address information becomes ``11'' as shown in Figure 5c, and the address information is determined. The circuit 9 makes a wrong judgment. Similarly, the delay element of the circuit causes the second and third units to
If the output of filter 7 ₁ corresponding to f ₁ is delayed, the address information will be incorrectly determined as "11" or "00" depending on the sampling clock signal, and this address information will be sent to discrimination circuit 9. Since the data is input as a signal different from the address information signal, the comparator circuit 12 shown in FIG. 4 has the disadvantage that it is not compared as accurate data, resulting in erroneous judgments and malfunctions.

The present invention has been provided in view of the above points, and has been provided for the purpose of preventing malfunctions due to noise and circuit delay elements.

Embodiments of the present invention will be described in detail below with reference to the drawings. As shown in FIG. 7, an address information judgment circuit 17 is inserted between the signal input circuit 14 of the discrimination circuit 9 in FIG. It has returned to Japan on the 14th. That is, as shown in Figure 8a, when noise N occurs in the output of the filter ₇₂ corresponding to the frequency _f2 in the first unit, and the circuit delay occurs in the second and third units. When the output of the filter ₇₁ corresponding to the frequency _f1 is delayed due to the element, it is sampled by the clock signal shown in FIG. 8b and the address information is "11" as shown in FIG. When the outputs of filters 7 ₁ and 7 ₂ such as ``11'' and ``00'' are detected at the same time, or when the outputs of filters 7 ₁ and 7 ₂ that are ``00'' are not detected at the same time, the clock signal that detects ``11'' and ``00'' For example, 0.2 msec after the time , the address information signals output from the filters 7 ₁ and 7 ₂ are detected again using the sampling signal Ss shown in FIG. 8b. Then, the normal outputs of the filters 7 ₁ and 7 ₂ are detected without the delay caused by the noise N and delay elements of the circuit. Then, normal data is read into the shift register 10 and it functions normally as described above.

As described above, in the present invention, when the outputs of a plurality of filters are detected, or when the outputs of two or more filters are detected, or when the outputs of none of the filters are detected, the clock signal is used to detect the clock signal for a certain period of time. Since the address information signal is later detected again using another sampling signal, it is possible to misjudge the address information signal due to noise or circuit delay factors.
This has an extremely excellent effect of eliminating malfunctions as much as possible.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a conventional address information signal, Fig. 2 is a block diagram showing the overall configuration of the same as above, Figs. A block diagram illustrating the functional operation of the discriminating circuit shown in FIG.
7 is a block diagram illustrating the functional operation of the discrimination circuit of the present invention. FIGS. 1 is a transmitter, 2 is a receiver, 3 is a load, 7 ₁ and 7 ₂ are filters, 9 is a discrimination circuit, 10 is a shift register, Tw
is the unit switching period, and Ss is the sampling signal.

Claims (1)

[Claims] 1 One or more transmitters and multiple receivers are provided, and an address information signal created by allocating a combination of multiple types of frequency signals to each unit time of multiple units without fail. a plurality of filters for discriminating the frequency components of each frequency signal included in the address information signal; A shift register that reads and stores the output status of each of the above filters in synchronization with a clock signal generated at approximately the same cycle as the unit switching cycle on the machine side, and a shift register that reads and stores the output status of each of the above filters, and assigns the received data stored in these shift registers to its own receiver. In a multi-channel remote control system equipped with a discrimination circuit that activates a load by detecting a match between the address setting data and the input address setting data, when the outputs of the plurality of filters are detected by a certain clock signal, , when the outputs of two or more filters are simultaneously detected, or when the outputs of none of the filters are detected, the address information signal is detected again using another sampling signal after a certain time from the clock signal. A multi-channel remote control system featuring: