JPH05207008A - Frame synchronization circuit - Google Patents

Abstract

PURPOSE:To optimally control a clock phase even in the case that the changing point of a preamble bit is not normally detected because of a noise, etc., in the frame synchronization detection of a burst signal with the preamble bit and a frame bit. CONSTITUTION:A frame synchronization circuit detects the changing point of a received signal by a changing point detecting part 1, and simultaneously, it detects a specified pattern in a preamble bit string by a specified pattern detecting part 3, and executes the logical operation of the detected results of both, and at the time of coincidence, it makes a clock phase control part 17 to be operated by a clock signal operate. Since the clock phase is controlled on the condition of the detection of the specified pattern in this way, the phase of the clock signal can be controlled optimally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit for processing a burst signal having a preamble bit and a frame bit.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional frame synchronization circuit for detecting synchronization from a burst signal. In FIG. 5, the change point detection unit 21 detects a change point of the data signal from the preamble bit included in the reception signal 25 which is a burst signal, and generates a change point detection pulse 28. The oscillator 22 generates a clock signal 26 having an oscillation frequency n times the received signal. With the clock signal 26 from the oscillator and the change point detection pulse 28 from the change point detection section 21, the clock phase control section 23 outputs the output clock signal 27 controlled to the optimum phase with respect to the received burst signal 25. The frame detector 24 detects a frame from the received signal 25 by using the output clock signal 27 of the clock phase controller 23.

[0003]

In this conventional frame synchronization circuit, the optimum phase is selected by n multi-phase clock signals in the preamble bit. Therefore, if the change point detection unit of the preamble information malfunctions due to noise or the like, there is a drawback that the phase shifts from the optimum phase.

Therefore, the technical problem of the present invention is to establish the frame synchronization by the clock controlled to the optimum phase when the preamble bit string is normally detected, and to detect the change point of the preamble bit due to noise or the like. It is an object of the present invention to provide a frame synchronization circuit capable of preventing malfunction.

[0005]

In order to solve the above-mentioned problems, the frame synchronization circuit of the present invention detects a change point by detecting a change point by reading a received signal having a preamble bit having a predetermined specific portion. A change point detection section, an oscillator for generating a clock signal having an oscillation frequency n times the frequency of the received signal, and a phase of the clock signal based on the clock signal and the change point detection signal In a frame synchronization circuit including a clock phase control unit that outputs a phase-controlled output clock signal, and a frame detection unit that detects the frame of the received signal by the output clock signal, Detect a specific part of the received signal,
A specific pattern detection unit that outputs a specific pattern detection signal indicating that the specific portion has been detected, and a logic unit that outputs a coincidence pulse of the change point detection signal and the specific pattern detection signal to the clock phase control unit. It is characterized by having.

In the frame synchronization circuit of the present invention, the clock phase control section outputs a preliminary phase clock signal based on the output from the logic means, and the preliminary phase clock signal. And a second clock phase control for outputting the output clock signal to the frame detection unit, which is controlled by the preampule bit detection unit that reads the received signal based on It is characterized by having a section and.

Further, in the frame synchronization circuit of the present invention, the change point detection section reads the received signal at the timing of the clock signal.

[0008]

In the frame synchronizing circuit of the present invention, the change point detection unit reads the received signal at the timing of the clock signal from the oscillator, detects the change point in the received signal, and outputs the change point detection signal. In addition, the specific pattern detection unit detects a specific portion of the preamble pulse of the received signal based on the clock signal from the oscillator, and outputs a specific pattern detection signal indicating that the specific portion has been detected. The logic means outputs a coincidence pulse with the change point detection signal and the specific pattern detection signal to the clock phase control section.
The clock phase controller includes a first clock phase controller,
It includes a preamplifier bit detector and a second clock phase controller. The first clock phase control section outputs the preliminary phase clock signal based on the output from the logic means. Based on this preliminary phase clock signal, the preamble bit detection unit reads the received signal and detects the preamble bit. The second clock phase controller is
The output clock signal is output to the frame detection unit under the control of the preamble bit detection unit.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the frame synchronization circuit according to the embodiment of the present invention includes a change point detection unit 1, an oscillator 2, a clock phase control unit 17, and a frame detection unit 8. The change point detection unit 1 shown in the figure detects the change point of the preamble bit of the received signal 9 which is a burst signal and generates the change point detection pulse 11 as in the conventional example of FIG. Further, the oscillator 2 generates a clock signal 10 having an oscillation frequency nf _o (f _o indicates a transmission rate) which is n times the received signal 9.

The frame synchronization circuit of FIG. 1 differs from that of FIG. 5 in that it has a specific pattern detection circuit 3 and also has a NAND circuit 4 as a logic means. The specific pattern detection circuit 3 generates a specific pattern detection pulse 12 when detecting a portion having a duty ratio of 50% in the preamble bit of the received signal 9. The specific pattern detection pulse 12 and the change point detection pulse 11 are subjected to a NAND operation in the NAND circuit 4 and the operation result is a coincidence pulse 13
Is output to the clock phase controller 17.

Further, the illustrated clock phase controller 17
Includes a first clock phase control unit 5, a preamble bit detection unit 6 and a second clock phase control unit 7,
First clock phase control unit 5 reads the clock signal 10 is loaded in by the coincidence pulse 13 frequency nf _o. The preamble bit detector 6 detects a preamble bit (for example, 1010101010101010) of the reception signal 9 at the timing of the preliminary phase clock signal 14 which is the output of the first clock phase controller 5 and outputs a preamble bit detection pulse 15. To do. The second clock phase control unit 7 uses the preamble pulse detection pulse 1
5 is optimum phase for the received signal 9 by the output f _o
Output clock signal. The frame detection circuit 8 detects the frame in again read a received signal received signal 9 at the output f _o clock signal.

Next, the operation of the frame synchronization circuit shown in FIG. 1 will be described with reference to FIGS. FIG. 2 shows a burst signal. As shown in the figure, the burst signal is
All have the same bit configuration, and the preamble bit 31 consisting of m bits at the beginning is followed by the frame bit 32 and the data bit 33.

FIG. 3 shows a signal input to the change point detection section. As shown in FIG. 3, the change point detector 1 detects a change point in the preamble bit from the received signal 9. FIG. 4 shows signals input to the specific pattern detection circuit 3.

As shown in FIG. 4, the specific pattern detection circuit 3 detects the portion where the duty ratio of the pulse of the preamble bit of the received signal is 50% by the clock signal from the oscillator 2. The first clock phase controller 5 controls the phase of the clock signal at the timing when the outputs from the two detectors match. The output of the first clock phase control unit 5 causes the preamble bit detection unit 6 to detect m preamble bits from the received signal 9. When all the conditions of the three detection units of the change point detection unit 1, the specific pattern detection unit 3, and the preamble bit detection unit 6 are satisfied, the second clock phase control unit 7 operates and the output clock signal of the optimum phase is output. It The frame detection unit 8 reads the received signal and detects a frame by the output clock signal having the optimum phase.

[0016]

As described above, according to the present invention, the preamble bit detector and the specific pattern detector are provided so that the output clock signal controlled to the optimum phase when the preamble bit string is normally detected. Establishes frame synchronization. Therefore, it is possible to provide a frame synchronization circuit capable of preventing a malfunction of detection of a change point of a preamble bit due to noise or the like.

[Brief description of drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a diagram showing an example of a burst signal.

FIG. 3 is a diagram showing an example of change point detection.

FIG. 4 is a diagram showing an example of detection of a specific pattern.

FIG. 5 is a configuration diagram of a conventional technique.

[Explanation of symbols]

 1, 21 Change Point Detection Unit 2, 22 Oscillator 3 Specific Pattern Detection Unit 4 NAND Circuit 5 First Clock Phase Control Unit 6 Preamble Bit Detection Unit 7 Second Clock Phase Control Unit 8, 24 Frame Detection Unit 9, 25 Received signal 10, 26 Clock signal 11, 28 Change point detection pulse 12 Pattern detection pulse 13 Matching pulse 14 Preliminary phase clock signal 16, 27 Output clock signal 15 Preample bit detection pulse 17, 23 Clock phase control unit 31 Preamble bit ( m bits) 32 frame bits 33 data

Claims (3)

[Claims] 1. A change point detection unit that reads a received signal having a preamble bit having a predetermined specific portion, detects a change point and outputs a change point detection signal, and an oscillation frequency n times the frequency of the received signal. An oscillator for generating a clock signal having a clock signal, a clock phase control unit for controlling the phase of the clock signal based on the clock signal and the change point detection signal, and outputting an output clock signal whose phase is controlled, and the output clock signal A frame synchronization circuit having a frame detection unit for detecting a frame of the received signal by a specific pattern detection signal indicating that a specific portion of the received signal is detected based on the clock signal and the specific portion is detected. Matching pulse between the specific pattern detection unit for outputting and the change point detection signal and the specific pattern detection signal And a logic means for outputting to the clock phase control unit. 2. The frame synchronization circuit according to claim 1, wherein the clock phase control section outputs a preliminary phase clock signal based on an output from the logic means, and the preliminary phase. A pre-ampoule bit detector that reads the received signal based on a clock signal and detects the pre-ampoule bit, and a second clock that is controlled by the pre-ampoule bit detector and outputs the output clock signal to the frame detector. A frame synchronization circuit comprising: a phase control unit. 3. The frame synchronization circuit according to claim 1, wherein the change point detection unit reads the received signal at the timing of the clock signal.