JPS637636B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a device for preventing malfunction of a timepiece, in particular, a control switch means for validating or disabling the operation of an operation switch for adjusting the time. The present invention relates to an improvement in forcibly disabling the operation of an operation switch if the operation switch or the control switch is not operated within a certain period of time.

With the recent development of LSI, LCD, switches, etc., watches are becoming lighter and smaller, and many of them have excellent designs. It's spreading.

Conventional clocks using a liquid crystal display or the like are mainly equipped with push-type, touch-type, or other operating switches to adjust the time. Due to the nature of the operation switch, the operation switch is easily operated, and there is a fear that it may easily malfunction, so a control switch is provided that disables operation of the operation switch except when adjusting the time.

Push-type switches are now often used for this control switch, and when the corrective operation is invalid, the corrective operation is enabled by operating the control switch, and conversely, when the corrective operation is valid, the same switch is operated. It was configured to disable modification operations. In addition, in order to prevent the correction operation from remaining in effect due to forgetting to operate the control switch,
It was configured so that if the operation switch or control switch was not operated for a set period of time, the correction operation was forcibly disabled.

However, if the correction operation takes a long time, for example if an emergency arises during the correction operation and the watch is temporarily left unattended, one has to be careful about how long it will take for the correction to become invalid.

The present invention is intended to solve the above-mentioned problems, and it is an object of the present invention to prevent the user from worrying that the correction will become invalid even if the correction operation takes a long time.

In order to achieve the above object, the present invention is characterized in that a warning sound is generated a predetermined time before the correction operation is forcibly disabled from the valid state.

Preferred embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a preferred embodiment of a time adjustment device to which a timepiece malfunction prevention device according to the present invention is applied.

A high frequency signal from a reference signal generation circuit 10 including a crystal oscillator etc. is converted into a desired frequency-divided pulse train by a frequency dividing circuit 12, and this frequency divided pulse is timed by a clock circuit 14 to display seconds, minutes, and hours. The signal is supplied as a clock signal via a decoder/driver 16 to a display section 18 made of a liquid crystal or the like to display the time.

The time adjustment circuit 19 is operated by operation switches 20, 22,
24, chattering prevention circuit 26, 28, 30,
It consists of AND gates 32, 34, and 36. The output of the operation switch 20 is connected to a chattering prevention circuit 26,
The signal is supplied through the AND gate 32 to a reset terminal of a second counter (not shown) in the timekeeping circuit 14, and the second counter is reset by operating the operating switch 20. In addition, the output of the operation switch 22 is output from the chattering prevention circuit 2.
8. The output of the operation switch 24 is sent to the clock terminal of a minute counter (not shown) in the timekeeping circuit 14 via an AND gate 34, and the output of the operation switch 24 is also sent to the clock terminal of a minute counter (not shown) in the timekeeping circuit 14 via an AND gate 36.
The minute signal and hour signal are respectively supplied to the clock terminal of an hour counter (not shown) within the clock, and the minute signal and hour signal are corrected by operating operation switches 22 and 24, respectively. Further, the _Q11 output of the flip-flop 124 in the control switch circuit 108 is supplied to the other input terminals of the AND gates 32, 34, and 36, and only when this correction operation enable signal is output, the operation switch 2
Operations 0, 22, and 24 become valid.

In this embodiment, a sound generation means is provided, and if the operation switch or control switch is not operated within a set time after the operation switch becomes valid (hereinafter referred to as the valid state) by the control switch means. A sound generation circuit 97 and a release warning time counting circuit 107 are provided to operate the sound generation means and generate a sound warning sound. In this embodiment, the operation switch is operated within the set time after becoming effective, and the control switch is operated by the control switch while the correction warning time counter is counting. An additional feature is that even when the operation is not invalidated (hereinafter referred to as invalid state), the sound generating means is operated to generate an audio warning sound. For this reason, the warning time counter includes a corrected warning time count circuit 77.

The sound generation circuit 97 as a warning sound generation circuit selects the sound signal generation circuit 40, the "ROCK SALE MASS" code ROM 98 for reading out the sound, the "KAIJIYO SALE MASHITA" code ROM 42 and the "KAIJIYO SALE MUSHITA" code ROM 44, and the code signal. a digital multiplexer 46 for operating the audio signal generating circuit 40, flip-flops (hereinafter abbreviated as FF) 48 and 100, OR gates 50, 102, 104, 106 and an AND gate 5 for operating the audio signal generating circuit 40.
2, an FF 54 and an OR gate 56, a one shot circuit 58, an amplifier 60 and a speaker 62. In order to generate an audio warning sound, the digital multiplexer 46 includes an audio signal generation circuit 40.
Code signals for reading out the voices "Kaijiyosaremashita" and "Kaijiyosareteimus" are supplied from the "Rotsukusaremas" code ROM 98, "Kaijiyosaremashita" code ROM 42, and "Kaijiyosareteimus" code ROM 44. . In addition, the digital multiplexer 46
The Q ₂ output of FF48 and the Q ₂ ' output of FF100 are supplied, and the Q ₂ output of FF48 is "H", and the FF10
When the Q ₂ ' output of 0 is "L", the code is "Kaijiyosaremasita"; similarly, when it is "L" and "H", it is "Kaijiyosaremasita"; when it is "H", "H", it is "Lotsukusaremasita". The signal is supplied to an audio signal generation circuit 40. Furthermore, the address pulse φa is supplied from the frequency dividing circuit 12 to the audio signal generating circuit 40 via an AND gate 52.
The Q ₁ output of FF 54 is supplied to the other input terminal of FF 54. Therefore, when the _Q1 output is "H", the AND gate 52 is opened and the address pulse φa is supplied to the audio signal generation circuit 40, and the audio signal selected by the code signal is generated by the address pulse φa. The audio signal is accessed and provided to a speaker 62 via an amplifier 60. When the audio signal access is completed, the audio end signal 40a is sent to the FF5 via the one-shot circuit 58.
The address pulse φa is supplied to the reset terminal _R1 of No. 4, and the supply of the address pulse φa ends. Therefore, when FF54 is set, the _Q2 output of FF48 and the Q2 output of FF100 are
Q ₂ ′The audio warning tone selected depending on the output status is
The signal is generated from the speaker 62.

On the other hand, the cancellation warning time count circuit 107 includes a 32-second counter 64, an AND gate 66, an FF 68, and an OR gate 7 that control the operation of the 32-second counter 64.
Consists of 2. Clock input for 32 second counter 64
A frequency dividing circuit 12 is connected to _C4 via an AND gate 66.
A clock pulse φc is supplied from the AND gate 66, and the Q ₃ output of the FF 68 is supplied to the other input terminal of the AND gate 66. Further, a signal 76a from a one-shot circuit 76, which will be described later, is supplied to a reset terminal R4 of the 32-second counter ₆₄ and a set terminal _S3 of the FF 68. The Q ₄ output of the 32 second counter 64 is supplied via the OR gate 72 to the reset terminal R ₃ of the FF 68 and to the OR gates 56 , 102 and 104 as an operation start signal for the sound generation circuit 97 .

Further, the corrected warning time count circuit 77 includes an OR gate 78 that receives the outputs of the AND gates 32, 34, and 36, an 8-second counter 80 that counts the corrected warning time, and an AND gate 82 that controls the operation of the 8-second counter 80. and FF84, AND gate 86 that controls the output of the 8 second counter 80
It consists of The clock input _C6 of the 8-second counter 80 is connected to the frequency divider circuit 1 via an AND gate 82.
Clock pulse φc is supplied from _Q5 of FF84 to the other input terminal of AND gate 82.
Output is supplied. Further, the output of the OR gate 78 is supplied to the reset terminal _R6 of the 8-second counter 80 and the set terminal _S5 of the FF 84, and the corrected warning time is counted by the corrected signal 78a. And _Q6 output of 8 second counter 80 is FF84
The signal is supplied to the OR gates 56, 102, and 104 of the audio generation circuit 97 via the reset terminal _R5 of the signal generator and the AND gate 86. Therefore, 8 seconds counter 8
The sound generation circuit 97 starts operating due to the _Q6 output of 0, and the operation of the corrected warning time counting circuit 77 is stopped. Also, at the other input terminal of the AND gate 86,
The _Q11 output of FF124 is supplied, and when the correction operation valid signal is not output, the Q11 output is sent to the audio generation circuit 97.
The _Q6 output of the second counter 80 is prohibited.

The recovery time counting circuit 87 includes a 64 second counter 88 for counting the recovery time, an AND gate 90, an FF 92, and an OR gate 94 for controlling the operation of the 64 second counter 88. 64 seconds counter 8
A clock pulse φc from the frequency dividing circuit 12 is supplied to the clock input C ₈ of the FF 8 through an AND gate 90, and the Q ₇ output of the FF 92 is supplied to the other input terminal of the AND gate 90. The output of the OR gate 94 is supplied to the reset terminal R ₈ of the 64 second counter 88 and the set terminal S ₇ of the FF 92 . Also, the or gate 94 has a 32 second counter 64.
Since the Q ₄ output and the correction signal 78a are supplied, the 64 second counter 88 starts counting the recovery time by the Q ₄ output of the 32 second counter 64 or the correction signal 78a. Further, the Q8 output of the 64 second counter ₈₈ is supplied to the reset terminal _R7 of the FF 92 and an OR gate 126 in the control switch circuit 108, which will be described later.

The decoder 96 constitutes a warning detection circuit that detects a specific warning setting value, "60" in this embodiment, before the output _Q8 of the 64 second counter 88 becomes "H" and outputs a warning detection signal to the signal 96a. do.

The control switch circuit 108 is a control switch 110
Operation switch 2 can be activated by pressing and holding for 3 seconds.
It is configured to enable or disable operations 0, 22, and 24. The output of the control switch 110 is supplied to the FF112, and the output of the FF112 is
The _Q9 output is supplied to the AND gate 114, and _{the Q9} output is supplied to the reset terminal _R10 of the 3 second counter 116. And clock input of 3 second counter 116
A _clock pulse φc is supplied from the frequency dividing circuit 12 to C10 via an AND gate 114, and the _Q10 output of the 3-second counter 116 is supplied to the shift register 11.
8 clock input Co. When the first clock pulse is input to the shift register 118, the Q ₀₁ output is output, and the FF 124 is set to the set state via the one-shot circuit 120, and the second clock pulse is input.
When the first clock pulse is input, the _Q02 output is output and the FF 124 is reset via the one shot circuit 122 and the OR gate 126. The output of the OR gate 126 is also supplied to the reset terminal R ₀ of the shift register 118 and the OR gate 72 in the release warning time counting circuit 107 . The Q ₁₁ output of the FF 124 is supplied to AND gates 32, 34, and 36, and controls whether the operation switches 20, 22, and 24 are enabled or disabled. Furthermore, the Q ₁₁ output of the FF 124 is supplied to a one-shot circuit 76, and a signal 76a from the one-shot circuit 76 is supplied to a sound generation circuit 97 and a release warning time counting circuit 107. Therefore, if control switch 110 is held down for 3 seconds, FF 124 is set.
Since _Q11 output becomes "H", operation switch 20,
Operations 22 and 24 become effective. Further, the operation of the sound generation circuit 97 and the release warning time counting circuit 107 is started by the signal 76a of the one shot circuit 76. Then, when the control switch 110 is held down for 3 seconds, the FF 124 is reset and the Q ₁₁ output becomes "L", so the operation switch 2
Operations 0, 22 and 24 are disabled.

FIG. 2 shows the first part of the malfunction prevention device according to the embodiment.
A time chart showing an example of operation is shown. The first example of operation is, for example, when the user forgets to disable the time adjustment after completing the time adjustment.

When the control switch 110 is pressed and held for 3 seconds to become effective, the _Q2 output is "H" and the _Q2 ' output is "L", so a voice notification sound "Kaijiyosaremashita" is generated, and _Q3 Output goes from “L” to “H”
32 seconds counter 64 starts counting. However, when the correction signal 78a rises due to the operation of the operation switches 20, 22, and 24,
The _Q3 output is inverted from "H" to "L" and the count of the 32 second counter 64 is stopped. At the same time as this
The _Q5 output is inverted from "L" to "H" and the 8 second counter 80 starts counting. As mentioned above,
Correction signal 78a when the time was last corrected
8 seconds are counted from the rising edge of , and when 8 seconds are counted, the Q ₆ output rises and the Q ₅ output becomes "H".
The 8-second counter 80 stops counting. And within the above 8 seconds FF1
24 is reset and the AND gate 86 is not closed, the _Q1 output and the _Q'2 output are inverted from "L" to "H" and an audible warning sound "Kaijiyosaretaimasu" is generated. And 64 seconds counter 88
When 60 seconds have elapsed in the valid state after starting counting, the signal 96a rises via the decoder 96, and the _Q1 output, _Q2 output, and _Q'2 output are inverted from "L" to "H" and the ” is generated. Furthermore, when the 64 second counter 88 starts counting and finishes counting for 64 seconds in the valid state, the _Q8 output rises and the _Q7 output is reversed from "H" to "L" and the count of the 64 second counter 88 is started. The _Q11 output is inverted from "H" to "L" via the OR gate 126. This closes AND gates 32, 34 and 36, rendering them inactive.

FIG. 3 shows a time chart showing a second operation example of the watch malfunction prevention device according to the embodiment. The second example of operation is, for example, a case where the active state is entered against the user's intention.

When the control switch 110 is pressed and held for 3 seconds at some time to become effective, the voice notification sound "Kaijiyosaremashita" is generated as described above.
The 32 second counter 64 starts counting. If the FF 68 is not reset by the operation of the control switch 110 while the 32 second counter 64 is counting, the _Q4 output will rise after 32 seconds and the _Q3 output will change from "H" to "L". ” and
The count of the 32 second counter 64 is stopped. Then, the _Q1 output and _Q'2 output are inverted from "L" to "H" and an audio warning sound "Kaijiyosaretimes" is generated. Furthermore, this _Q4 output inverts the _Q7 output from "L" to "H" and the 64 second counter 88 starts counting. Then, as mentioned above, 60 seconds after the 64-second counter 88 starts counting, the audio notification sound "Lotsukusaremasu" is generated.
It will be forcibly disabled after 64 seconds.

As described above, according to this embodiment, even if the user forgets to disable the time after completing the time adjustment, the audio warning sound is generated at the timing of the count time of the 8-second counter 80, that is, after 8 seconds. This has the effect of making it easier for the user to recognize that it is in the valid state. Furthermore, even if the device becomes active against the user's intention, it is possible to make the user recognize the active state by voice after 32 seconds. As described above, the present invention can also be applied to the above-mentioned time adjustment device for a clock that is forced to be in an invalid state. Furthermore, in this embodiment, an audio notification sound is generated to notify the user that the state will become disabled 4 seconds before the state is forced to become disabled, so if it takes a long time to adjust the time,
The effect is that the user can extend the effective state without using unnecessary care.

As described above, according to the present invention, by providing the warning detection circuit and the warning sound generation circuit, the warning sound is generated immediately before the correction operation is forcibly disabled, so that the user does not have to wait for a long time. Even when it comes to correction operations,
Since the corrective operation is not invalidated until the above-mentioned warning sound is generated, the corrective operation can be performed with peace of mind without unnecessary stress.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a preferred embodiment of a time adjustment device to which a timepiece malfunction prevention device according to the present invention is applied. FIG. 2 is a time chart showing an example of the operation of the watch malfunction prevention device according to the embodiment. FIG. 3 is a time chart showing a second operation example of the watch malfunction prevention device according to the embodiment. 10... Reference signal generation circuit, 12... Frequency dividing circuit, 1
4... Clock circuit, 16... Decoder driver, 18
...Display section, 19...Time correction circuit, 96...Decoder, 97...Audio generation circuit, 107...Warning time count circuit, 77...Modified warning time count circuit, 8
7...Return time count circuit, 108...Control switch circuit.

Claims (1)

[Scope of Claims] 1. A reference signal generating circuit that generates a reference signal, a frequency dividing circuit that divides the frequency of the reference signal, and a time reference signal output from the frequency dividing circuit that measures at least the hour and minute digits. a clock circuit that outputs a clock signal; a time display section that displays a time corresponding to the clock signal; and a time display section that is switched between a set state and a reset state in response to operation of a control switch, and that performs a corrective operation when in the set state. a control switch circuit that outputs a valid signal; a time adjustment circuit that supplies a correction signal to the timekeeping circuit in response to operation of the operation switch, with the output of the correction operation valid signal as a condition; and the control switch circuit in a set state. At this time, a constant period signal from the frequency dividing circuit is counted from an initial state in response to a signal based on the output of the correction operation valid signal or in response to the output of the correction signal, and this count value becomes a specific reset setting value. a return time count circuit that outputs a return signal that forcibly resets the control switch circuit when the control switch circuit is reset; A watch comprising: a warning detection circuit that outputs a warning detection signal upon detecting that the warning detection signal has reached a certain value; and a warning sound generation circuit that generates a warning sound in response to the output of the warning detection signal. malfunction prevention device.