JPS6380296A - Video signal processing circuit for driving liquid crystal panel - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal processing circuit used in a drive circuit for displaying video signals of a television or the like with high resolution and high gradation on a liquid crystal panel. It is something.

[Conventional technology]

To display video signals from a television or the like on a liquid crystal panel, for example, as shown in FIG. 5, a pixel is constructed of a thin film transistor 101 as a switch element on a glass substrate and a capacitor 102 using liquid crystal as a memory element. are arranged in an X-Y matrix, and a Y electrode 105 is connected to the gate electrode of the transistor 101 by a line sequential drive circuit 103.
There is a method in which a pulse voltage is applied through the X electrode 106, and a signal voltage is applied to the drain electrode by the video signal processing circuit 104 through the X electrode 106.

A conventional video signal processing circuit includes a number of sample and hold circuits corresponding to the number of pixels in the X direction in order to sample a video signal and convert it into a parallel signal. An example of this sample and hold circuit will be explained.

FIG. 6 shows its circuit diagram, and FIG. 7 shows a timing chart for explaining the operation.

In FIG. 6, 111 is a sample/hold circuit for sampling the video signal, and is composed of a transistor 113 and a signal storage capacitor 114. Further, 112 is a hold circuit that holds the signal voltage transferred from the sample-and-hold circuit 111 while it is being applied to the X electrode. A video signal a shown in FIG. 7 is input to a video signal input terminal 115 of the sample and hold circuit 111, and a sampling pulse b is applied to an input terminal 116.

A transfer pulse C is applied to an input terminal 118 of the hold circuit 112. Note that 120 in the figure is an output terminal.

In this video signal processing circuit, sampling pulses of different phases are input to a large number of sample/hold circuits corresponding to the number of pixels in the X direction, and the video signal is sequentially sampled.

[Problem that the invention seeks to solve]

The sampling time when sampling an NTSC video signal in a conventional video signal processing circuit is as follows: the number of pixels in the X direction is 300, and the effective horizontal scanning period is 52.5/
If J S, 52.5 #S ÷ 300 = 0.17
5 μs (sampling frequency 5.7 MHz).

However, manufacturing high-speed sampling circuits with a sampling frequency on the order of MHz with high precision and high yield in numbers of several hundred or more, which is the same as the number of pixels in the This is extremely difficult due to variations in the ON resistance of the signal storage capacitor 114 and the capacitance of the signal storage capacitor 114.

In particular, when increasing the number of pixels and increasing the sampling frequency to increase the resolution in the X direction of the display, the capacitance of the signal storage capacitor 114 must be reduced.
S/ due to switching noise of transistor 113, etc.
The N ratio decreases, and the variation in characteristics of each sample-and-hold circuit increases, which impedes gradation display.

An object of the present invention is to provide a video signal processing circuit for driving a liquid crystal panel that solves this problem.

[Means for solving problems]

The present invention provides a time-series video signal processing circuit for driving a liquid crystal panel for displaying gradations in a liquid crystal The video signal that is the signal is
A sample/hold circuit that samples at a frequency corresponding to the number of pixels in the direction nX, a reset circuit that converts the sampled continuous video signal into a pulse-like waveform, and a signal charge that corresponds to the pulse-like signal voltage. It is characterized by being equipped with an nX stage CCD shift register that sequentially transfers data.

[Effect]

The present invention basically provides high-speed, high-precision sample-and-hold circuits for sampling a video signal, which is a time-series signal, in a number corresponding to each color. The video signal sampled by the sample-and-hold circuit is converted into a pulse-like waveform by the reset circuit in order to be input to the subsequent CCD shift register. Then, the CCD shift register sequentially shifts the signal charges corresponding to the pulsed signal voltage using a shift pulse. Current CCD shift registers can be driven with a clock pulse frequency of about IOMH2 or higher, and signals from high-speed, high-precision sample-and-hold circuits can be reliably shifted sequentially. Clock pulse of sample/hold circuit and CCD shift register is 10MH
When operated at z, the number of pixels in the X direction is: effective horizontal scanning period 52.5 u s
Hz = 525, which is sufficient to display television images in black and white on an LCD panel, and even in the case of color, it is necessary to increase the clock pulse frequency even higher or to add a sample and hold circuit for each color signal. By using it, it is possible to display color images.

Furthermore, in the case of a conventional configuration using a large number of sample-and-hold circuits, it was necessary to apply sampling pulses of different phases to each sample-and-hold circuit separately, but in the case of the present invention, two Since it is only necessary to apply a clock pulse of approximately the same amount as the clock pulse to the CCD shift register, the circuit configuration is simplified. Furthermore, variations in characteristics that occur when there are a large number of sample-and-hold circuits corresponding to the number of pixels in the X direction, as in the conventional case, are reduced, making it possible to display high gradations.

The video signal for one horizontal scanning line is sampled and sent to the CCD.
When shifted in the shift register, all transfer gates are turned on at the same time, and the signal charge in the CCD shift register is transferred to the hold capacitor, and after being amplified to the required voltage by the buffer amplifier, it is transferred to the X electrode of the liquid crystal panel. Output.

Note that the transfer gate and hold capacitor that transfer and hold signal charges in the CCD shift register are a type of sample-and-hold circuit, but since the transfer gate is turned on during the horizontal blanking period (approximately 11 μs), the sampling frequency is relatively low, about 100 kHz, so variations in the ON resistance of the transfer gate and the capacitance of the individual hold capacitors do not pose a problem.

〔Example〕

A video signal processing circuit for driving a liquid crystal panel capable of high gradation display will be described in detail below.

FIG. 1 shows the configuration of a video signal processing circuit for driving a monochrome display liquid crystal panel according to an embodiment of the present invention.

This video signal processing circuit includes a high-speed sample/hold circuit 1 having a storage capacitor 9, a reset circuit "12" consisting of transistors 2.3, and a CCD shift register 4.
It is composed of.

The transistor 2 of the reset circuit 12 is a gate transistor that inputs the signal charge corresponding to the video signal voltage accumulated in the storage capacitor 9 of the sample/hold circuit 1 to the CCD shift register 4, and the transistor 3 is turned on. During this period, the reset transistor operates to divide the signal charge for each pixel by setting the signal to O.

The CCD shift register 4 is composed of, for example, a buried channel type CCD shift register with high transfer efficiency, the number of shifts is nx corresponding to the number of pixels in the X direction, and the shift clock pulse φ8 and its opposite phase pulse L are Two-phase CCD with nX stages that shifts signal charges to the next stage every cycle
It is a shift register.

Since signal charges corresponding to the number of pixels nx are accumulated in the nX-stage two-phase CCD shift register 4, in order to transfer each signal charge to the corresponding hold capacitor 6 all at once,
, transfer gates 5 are connected. Also,
The hold capacitor 6 is provided with a discharging transistor 7 for resetting signal charges during the horizontal scanning period. Further, each hold capacitor 6 is connected to a corresponding buffer amplifier 8.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

A video signal a, which is a time-series signal, is input to the video signal input terminal IO. In the waveform of the video signal a in Fig. 2,
T indicates the Nth horizontal scanning period within one field, and Tb indicates the horizontal blanking period.

On the other hand, the input terminal 11 of the sample and hold circuit 1 has
A sampling pulse b is applied, and the sample/hold circuit 1 samples the video signal a based on the sampling pulse b. Signal d in FIG. 2 is a sampled video signal. The sampling frequency of the sampling pulse b is determined by the effective horizontal scanning period TV+the number of pixels in the X direction nX. The sampled video signal d is input to the reset circuit 12. A gate pulse e is applied to an input terminal 13 of the reset circuit, and a reset pulse r is applied to an input terminal 14 of the reset circuit. As shown in Figure 2,
The phases of these pulses e and f differ by 180'. The reset circuit 12 converts the sampled video signal d into a pulse waveform to be input to the CCD shift register 4, and inputs the pulse waveform to the CCD shift register 4. Signal g in FIG. 2 shows a video signal converted into a pulsed signal.

The shift clock pulse input terminals 16 and 17 of the CCD shift register 4 receive two-phase shift clock pulses φ.
9. ``?;1 is input respectively, and the reset/7 reset circuit 12
The signal charges corresponding to the pulsed video signal g from 1 to 2 are sequentially shifted. When the signal charge within the Nth horizontal scanning period is shifted in the CCD shift register, input terminal 1
A transfer gate pulse h is inputted from 8, and the transfer gates 5 are turned on all at once. The transfer gate 5 is turned on during the horizontal blanking period T after the sampling of the video signal and the shifting by the CCD shift register are completed within one horizontal scanning period.

It is within.

The signal charges of the nX stage CCD shift register 4 are n, x
The signal is transferred to the hold capacitor 6. Each hold capacitor 6 holds the signal charge within the Nth horizontal scanning period until the signal charge within the N+1st horizontal scanning period is transferred from the CCD shift register 4.

The outputs from the nX hold capacitors 6 are amplified by the corresponding n8 bass amplifiers 8 to a voltage necessary to drive the liquid crystal panel, and are output from the terminal 20 to the X electrode of the liquid crystal panel.

Then, the Nth corresponding Y electrode is selected and an image is displayed on the liquid crystal panel.

A reset pulse i is applied to the discharge transistor 7 from the input terminal 19, and the hold capacitor 6 is reset.

Next, FIG. 3 shows an embodiment of a video signal processing circuit for driving a liquid crystal panel for color display. This video signal processing circuit includes sample/hold circuits 31, 32, 33 corresponding to each color signal (R, G, B), gate transistors 51, 52, 53 and one reset transistor corresponding to each color signal. 57, and a reset circuit 50 consisting of C.
It is composed of a CD shift register 60.

FIG. 4 is a timing chart for explaining the operation of this embodiment. Video signals of each color are input to input terminals 41, 42, and 43, and sample and hold circuits 31, 32
．． The input terminals 44, 45, and 46 of 33 receive sampling pulses 1. m, n are input, and the sampled video signal 0. p.

q is output. In the reset circuit 50, in order to reduce switching noise in the sample and hold circuit,
The gate transistors 51, 52, and 53 are turned on when the sampled video signal has calmed down.
Gate pulses are applied to input terminals 54, 55° and 56, respectively. A reset pulse r is input to the input terminal 58 and converted into a pulse-like waveform S. The input terminals 61 and 62 of the CCD shift register 60 receive a shift clock pulse φ3. and its opposite phase pulse 71 are input, and the signal charges are sequentially shifted.

In this embodiment, since the signal charges in the CCD shift register are arranged in the order of R, G, B, the pixels of the liquid crystal panel are also arranged in the same order of <R, G, B.

〔Effect of the invention〕

As described in detail above, the video signal processing circuit for driving a liquid crystal panel according to the present invention uses a CCD shift register to suppress the use of high-speed sample-and-hold circuits that require high precision to within a few pieces, thereby reducing the variation in characteristics. It is possible to display high resolution and high gradation images on the LCD panel.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a video signal processing circuit for driving a monochrome display liquid crystal panel according to an embodiment of the present invention. ) FIG. 3 is a diagram showing the configuration of a video signal processing circuit for driving a color liquid crystal panel according to another embodiment of the present invention. FIG. Figure 5 is a diagram showing the configuration of a liquid crystal panel; Figure 6 is a diagram showing an example of a conventional video signal processing circuit; Figure 7 is a diagram showing an example of a conventional video signal processing circuit; 7 is a diagram showing a timing chart for explaining the operation of the video signal processing circuit of FIG. 6. FIG. 1... Sample/hold circuit 2... Gate transistor 3... Reset transistor 4... CCD shift register 5... Transfer gate 6... Hold capacitor 7... Discharge transistor 8. ...Paper amplifier 12, 50...Reset circuit 31...R sample/hold circuit 32...G sample/hold circuit 33...B sample/hold circuit 60...CCD shift register Representative Patent Attorney Yoshiyuki Iwasa Figure 1 bt, -1, Yu -"Tsui...SAN L"Tsui...
1'−−−−−−−−−−−'−'−゛. d video signal. e Gate Nokurusu LJUIII・ ・ ・ ・
・ ■匪-Jlflllf Reset pulse Jl[
・ ・ ・ ・ ・ n9 dJL 4 thick (this conversion
” ・ ・ , , ”]]■---1 Sahata video signal φ, ri 0tsuk pulse “LJlflfL・ ・ ・ −
Uh h 7 included knees. 2 1 Reset pulse Fig. 2 C Fig. 3 φ, clock pulse -11] Aim and method ■ Fig. 4 103 line sequential movement circuit Fig. 5

Claims (1)

[Claims] (1) In a video signal processing circuit for driving a liquid crystal panel for displaying gradations in a liquid crystal a sample/hold circuit that samples a video signal with a frequency corresponding to the number of pixels n_x in the X direction; a reset circuit that converts the sampled continuous video signal into a pulsed waveform; and the pulsed signal voltage. 1. A video signal processing circuit for driving a liquid crystal panel, comprising: an n_x stage CCD shift register that sequentially transfers signal charges corresponding to .