JPH07104708A - Drive device for data line of active LCD panel - Google Patents

Abstract

(57) [Abstract] [Objective] A ghost that occurs on the LCD panel surface is prevented by the overlap of the sampling signals of each bit of the shift register. [Structure] Between the shift register 1 and the sample and hold circuit 2, the rising edge of the sampling signal of each bit of the shift register 1 is delayed by at least the delay time of the output of the sampling signal and output to the sample and hold circuit 2. A delay circuit 5 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive device for an LCD (liquid crystal display) panel which is widely used as a display panel for an electronic device, and more particularly to a data line drive device for an active matrix type LCD panel.

[0002]

2. Description of the Related Art By adding an active element such as a transistor to each pixel of an LCD panel, high quality display capable of high gradation display can be performed, and such an LCD panel is called an active type LCD panel. FIG. 8 shows a general active LCD using a thin film transistor as an active element.
FIG. 11 is a circuit diagram showing a conventional example of a panel, which includes a plurality of scanning lines S (S ₁ , S ₂ , ... S _n ) and a plurality of data lines D (D ₁ , D ₂ , ... D _n ). 41 are provided at the respective intersections of the thin film transistor 42, the gate g of which is connected to the scanning line S and the source s thereof is connected to the data line D, and the drain d of the thin film transistor 42 and the reference voltage. A holding capacitor 44 formed between a terminal, for example, a ground terminal, and a liquid crystal 43 to which the voltage of the holding capacitor 44 is applied.

FIG. 9 shows an example of this active LCD panel.
FIG. 6 is an operation waveform diagram in a pixel lighting state,
T as shown in FIG. 9 (2).₀Period (frame period
(Referred to as "ma"), the wave height is inverted around the ground voltage.
Value v_dShort-wave AC signal voltage V_dThe scan line.
Frame S, as shown in FIG. 9 (1).₀Every
Output period T₁, Peak value v_sPulse wave signal voltage V
_sIs applied. The signal voltage V is applied to the scanning line S._sIs applied
Then, the thin film transistor 42 is turned on, and the holding capacitor 4
4 is the peak value v of the data line D_dSignal voltage V_dMark
The signal voltage of the scanning line S is added as shown in FIG.
Pressure V_sOutput period T₁Charged in the data line D
Signal voltage V_dPeak value v_dReach Scan line S
Signal voltage V _sOutput period T₁Thin film trans
Although the transistor 42 is turned off, the voltage of the holding capacitor 44 is
Voltage v due to the charged charge_dHold the next flare
Signal voltage V to scan line S_sIs applied,
Crest value inverted to taline D-v_dSignal voltage V_dBut
When applied, the voltage is inverted and the voltage is −v._dSwitch to. Retention
V of the capacitor 44_dFrom-v_dAC voltage changing to
Is applied to the liquid crystal 43 to be turned on. In addition, LC
The D panel is usually driven by an alternating voltage in this way.
(Driving with DC voltage causes irreversible deterioration, that is, electrical
Chemical changes will occur).

FIG. 10 is a circuit diagram showing a conventional example of a drive device for the data lines D (D ₁ , D ₂ , ... D _n ) of this type of active LCD panel. In FIG. 10, the driving device is an n-bit shift register 1 having a start signal terminal Q to which a start signal q consisting of one pulse is input and a clock signal terminal CK to which a clock signal ck having a predetermined number of pulses is input. , A video signal terminal P connected to this shift register and receiving a video signal p
, And an n-bit output buffer 3 connected to the sample-and-hold circuit 2. Output terminals D (D ₁ , D ₂ , ... · D _n), the data line D (D ₁ of the active matrix type LCD panel,
D ₂ , ... D _n ) respectively (see the circuit diagram of the active LCD panel shown in FIG. 8).

The operation of this drive circuit is as follows. The start signal q input to the start signal terminal Q of the shift register 1 is sequentially transferred between these bits for each pulse of the clock signal ck input through the clock signal terminal CK, and this clock signal is transferred. The sampling signals are sequentially output to the sample and hold circuit 2 from the selected bit. The sample hold circuit 2 samples and holds the video signal p input from the video signal terminal P at each bit at the output timing of each bit of the shift register 1. In addition, in general, the sample hold circuit 2
Includes two circuits, A and B, and the B circuit samples the data of the next scanning line while the A circuit outputs the sampled and held data. The impedance of the sample-held signal voltage is reduced by the output buffer 3, and the active type is used as the signal voltage V _d of the data line from each output terminal D (D ₁ , D ₂ , ... D _n ) of this output buffer 3. It is output to the data lines D (D ₁ , D ₂ , ... D _n ) of the LCD panel, respectively.

[0006]

Generally, a shift register
Is the same as the rising or falling edge of the clock signal.
Since the start signal is transferred in time, each bit is sequentially
The output sampling signal is shown in the operation waveform diagram of Fig. 11.
As described above, the delay time Δt of the output of the sampling signal₀of
Will be overlapped. In addition, the operation wave of FIG.
The figure shows the case of color display, output terminal D₁, D_Four，
D₇The signal voltage corresponding to the three primary colors red is output from
Terminal D₂, D_Five, D₈... Signal voltage corresponding to green
But output terminal D₃, D₆, D₉... corresponds to blue
The signal voltage is output, for example, the output terminal D₁Out
Force terminal D_FourSampling signal between or and output end
Child D _FourAnd output terminal D₇The sampling signal between
It causes a barrup. In this way, the sampling signal
Burlap causes interference between these two bits.
Cause a ghost, and the quality of image display deteriorates. 12
And FIG. 13 shows that due to the overlap of sampling signals
Fig. 12 shows the principle of ghosting.
Data line driving device for active color LCD panel
Fig. 13 is a circuit diagram of the main part showing the details of
Driven active type color LCD panel panel
The schematic diagram of a surface is shown. In FIG. 12, sample hold
The input terminal of the circuit 2 is the red terminal of the video signal terminal P
P_r, Green terminal P_gAnd blue terminal P_bIn order
Returned and connected, its output terminal is
Connected to the input terminals of the voltage follower 31
The sampling signal of each bit of the shift register 1
Analog switch 21 for each input bit
Between the output side of these analog switches 21 and ground.
It consists of a capacitor 22 for each bit connected to each
The output terminal of the voltage follower 31 for each bit is
Output terminal D of the output buffer 3 (D₁, D₂・ ・ ・ D
_n) Are connected respectively.

The analog switch 21 for each bit of the sample-hold circuit 2 is sequentially turned on by the sampling signal of each bit of the shift register 1, and the red terminal P _r , the green terminal P _g and the blue terminal P _{b of} the signal input terminal P are turned on. The red signal p _r , the green signal p _g, and the blue signal p _b of the input video signal p are sequentially repeated, and the capacitor 2 of each bit
Sample and hold to 2. The output impedance of the signal voltage sampled and held by the capacitor 22 of each bit is reduced by each voltage follower 31 of the output buffer 3, and the signal voltage V _d is output to the data line D of the active color LCD panel. .

Here, if the sampling signal of the shift register 1 overlaps, for example, if the sampling signal of the output terminal D _{1 and} the sampling signal of the output terminal D ₄ overlap, the output terminal D ₁ of Before the analog switch 21 is turned off, the analog switch 21 of the output terminal D ₄ is turned on, and as shown by an arrow H in FIG. 12, a circulating current flows between the capacitor 22 of the output terminal D _{1 and} the capacitor 22 of the output terminal D _4. And these capacitors 22
The value of the sampled and held signal voltage will change. Therefore, a dot image or a cross-shaped image indicated by dense diagonal lines in the schematic view of the panel surface shown in FIG. 13 has a ghost image indicated by arrows A or B and shown by coarse diagonal lines below two pixels by six pixels left. Cause The panel surface shown in FIG.
The data lines D (D ₁ , D ₂ , ... D _n ) are arranged alternately from the top and bottom in a comb shape, and the sample and hold circuit is 1
The case where the bit has two circuits of A and B is shown, and a ghost appears at the left of 6 pixels and 2 pixels below.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent a ghost which occurs on the LCD panel surface due to the overlap of the sampling signals of each bit of the shift register in the data line driving device of the active LCD panel.

[0010]

According to the present invention, a start signal and a clock signal are input, and the start signal is sequentially transferred between each bit for each pulse of the clock signal. Then, from a bit shift register that sequentially outputs a sampling signal from the bit to which this start signal is transferred, and a sample hold circuit for each bit that samples and holds the video signal by the sampling signal for each bit of this shift register In the device for driving the data line of the LCD panel, which outputs the signal voltage sampled and held by each bit of the sample and hold circuit to each data line of the active LCD panel, between the shift register and the sample and hold circuit. , The sampler for each bit of this shift register Delaying the rise of the grayed signal than the delay time of the output of the sampling signal provided a delay circuit for outputting to the sample-and-hold circuit. In this delay circuit, the sampling signal of each bit of the shift register is input to one input terminal, the sampling signal is input to the other input terminal through an inverter connected in series, and the output terminal is It is preferable to use an AND gate for each bit connected to each bit of the sample and hold circuit, or the sampling signal for each bit of the shift register is
It is preferable that the AND circuit includes an AND circuit that outputs to each bit of the sample and hold circuit under an AND condition with the control signal that falls at the same time as the clock signal and rises after a delay time of the output of the sampling signal or more.
Further, the control signal may consist of a clock signal.

[0011]

In the data line driving device of the active type LCD panel of the present invention, the rising edge of the sampling signal of each bit of the shift register is delayed between the shift register and the sample hold circuit by delaying the output of the sampling signal. Since a delay circuit for delaying more than time and outputting to the sample hold circuit is provided, the rising edge of the sampling signal of each bit is delayed by the delay time of this sampling signal or more, and an overlap occurs between the sampling signals of each bit. It will never happen. In this delay circuit, the sampling signal of each bit of the shift register is input to one input terminal, the sampling signal is input to the other input terminal through an inverter connected in series, and the output terminal is With the AND gate of each bit connected to each bit of the sample hold circuit, the rising edge of each sampling signal is delayed by the delay time of these inverters. An AND that outputs the sampling signal of each bit of the shift register to the sample and hold circuit by taking an AND condition with the control signal that falls at the same time as the clock signal and rises after the delay time of the output of the sampling signal is exceeded. By configuring the delay circuit with the circuit, the rising edge of the sampling signal of each bit is delayed by the time between the falling edge and the rising edge of the control signal to cause overlap between the sampling signals of each bit. Disappears. Further, the clock signal can be used as a control signal because the time between its falling edge and its rising edge is usually longer than the delay time of the output of the sampling signal.

In this way, it is possible to prevent the ghost that occurs on the LCD panel surface due to the overlap between the sampling signals of each bit.

[0013]

1 is a circuit diagram showing an embodiment of a data line driving device of an active LCD panel according to the present invention. The data line driving device of the active LCD panel of the present invention shown in FIG. 1 is the same as the data line driving device of the conventional active LCD panel shown in FIG.
A delay circuit 5 is provided between the shift register 1 and the sample hold circuit 2. The delay circuit 5 has an even number of 4 bits in FIG. 1 in which the sampling signal of each bit of the shift register 1 is input to one input terminal and the sampling signal is connected in series to the other input terminal.
Each of the inverters 52, 53, 54 and 55 is input to the output terminal of the sample and hold circuit 2, and the AND gate 51 is connected to each bit of the sample and hold circuit 2.

The operation of the data line driving device of the active LCD panel will be described with reference to the operation waveform chart shown in FIG. The operation waveform diagram shown in FIG. 6 corresponds to the operation waveform diagram of the conventional data line driving device of the active LCD panel shown in FIG. 11, and the sampling signal of each bit from the shift register 1 in FIG. ,
The respective rising edges are delayed by the delay circuit 5 for a time Δt ₁ longer than the delay time Δt ₀ of these sampling signals and input to the sample hold circuit 2. In this way, there is no overlap of the sampling signal between the output terminals D ₁ and D ₄ or the sampling signal between the output terminals D ₄ and D ₇ . By this, L
Ghosting on the CD panel surface can be prevented.

FIG. 2 is a circuit diagram showing another embodiment of the data line driving device of the active LCD panel of the present invention. Generally, the signal voltage V _d for driving the data line of the active LCD panel, which is output from the output terminal D of the output buffer 3, is higher than the logic voltage of the 5V system, for example, a voltage of several tens of volts. In the embodiment shown in FIG. 3, a level shifter 7 for converting the output signal from the shift register 1 into a high voltage system is provided between the shift register 1 and the delay circuit 5, and the signal voltage output from the output terminal D of the output buffer 3 is provided. It is a boosted version of V _d . The level shifter 7 may be provided between the delay circuit 5 and the sample hold circuit 2.

FIG. 3 is a circuit diagram showing still another embodiment of the data line driving device of the active LCD panel according to the present invention. FIG. 3 shows the drive device shown in FIG. 1 in which an AND circuit 6 is provided instead of the delay circuit 5. In the AND circuit 6, the sampling signal of each bit of the shift register 1 is input to one input terminal, the control signal r from the control terminal R is input to the other input terminal, and the output terminal is connected to the sample hold circuit 2. The AND gate 61 of each bit is connected to each of the bits.

The operation of the data line driving device of the active LCD panel will be described with reference to the operation waveform diagram shown in FIG. The operation waveform diagram shown in FIG. 7 corresponds to the operation waveform diagram of the data line driving device of the conventional active type LCD panel shown in FIG. 11, and from the control terminal R in FIG. Clock signal c as shown
A control signal r that falls at the same time in synchronization with k and rises after a time Δt ₁ longer than the delay time Δt ₀ of the sampling signal output is input. This control signal r is supplied to the AND circuit 6
Is input to the other terminal of each AND gate 61 and the AND condition of this control signal r and the sampling signal from the shift register 1 is taken. This AND condition, the sampling signal of the output terminal D ₁ of the shift register 1 shown in FIG. 7 (3), for example, its rise as shown in FIG. 7 (4) is delayed for a time Delta] t _1,
It is input to the sample hold circuit 2. Also, FIG.
The sampling signals at the output terminals D ₄ and D ₇ shown in (5) and (6) are also delayed by the rising time Δt ₁ thereof and input to the sample hold circuit 2.
In this way, there is no overlap of the sampling signal between the output terminals D ₁ and D ₄ or the sampling signal between the output terminals D ₄ and D ₇ .

FIG. 4 is a circuit diagram showing a different embodiment of the data line driving device of the active LCD panel of the present invention. 4 eliminates the control terminal R in FIG. 3,
To the other terminal of each AND gate 61 of the AND circuit 6,
The clock signal cr input to the terminal CR of the shift register 1 is input. Since the time between the falling edge and the rising edge of the clock signal is longer than the delay time of the output of the normal sampling signal, the rising edge of the sampling signal can be similarly delayed.

FIG. 5 is a circuit diagram showing a different embodiment of the data line driving device of the active LCD panel of the present invention. FIG. 5 shows that the shift register 1 is provided between the shift register 1 and the AND circuit 6 in the driving device shown in FIG.
The level shifter 7 for converting the output signal from the output buffer 3 into a high voltage system is provided to boost the signal voltage V _d output from the output terminal D of the output buffer 3. The level shifter 7 may be provided between the AND circuit 6 and the sample hold circuit 2. The level shifter 7 is shown in FIG.
The same can be provided in the driving device shown in FIG.

[0020]

According to the data line driving device of the active LCD panel of the present invention, the ghost generated on the LCD panel surface is prevented by the overlap of the sampling signals of each bit of the shift register, so that the image quality is remarkable. Improve significantly.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a data line driving device of an active LCD panel according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of a data line driving device of an active LCD panel according to the present invention.

FIG. 3 is a circuit diagram showing a different embodiment of the data line driving device of the active LCD panel of the present invention.

FIG. 4 is a circuit diagram showing a different embodiment of the data line driving device of the active LCD panel of the present invention.

FIG. 5 is a circuit diagram showing still another embodiment of the data line driving device of the active LCD panel of the present invention.

6 is an operation waveform diagram of a data line driving device of the active LCD panel of the present invention shown in FIG.

7 is an operation waveform diagram of a data line driving device of the active LCD panel of the present invention shown in FIG.

FIG. 8 is a circuit diagram of a general active LCD panel.

9 is an operation waveform diagram of one pixel of the active LCD panel shown in FIG.

FIG. 10 is a circuit diagram showing an example of a data line driving device of a conventional active LCD panel.

11 is an operation waveform diagram of a data line driving device of the conventional active LCD panel shown in FIG.

FIG. 12 is a circuit diagram of a main part showing details of a conventional data line driving device of an active color LCD panel.

FIG. 13 is a schematic view of a panel surface of a conventional active color LCD panel.

[Explanation of symbols]

 1 shift register 2 sample hold circuit 5 delay circuit 51 AND gate 52 inverter 53 inverter 54 inverter 55 inverter 6 AND circuit

Claims (4)

[Claims] 1. A start signal and a clock signal are input, the start signal is sequentially transferred between each bit for each pulse of the clock signal, and a sampling signal is sequentially output from the bit to which the start signal is transferred. It consists of a multi-bit shift register and a sample and hold circuit for each bit that samples and holds the video signal by the sampling signal of each bit of this shift register, and the signal voltage sampled and held by each bit of this sample and hold circuit is activated. In a device for driving a data line of an LCD panel for outputting to each data line of a type LCD panel, a rising edge of a sampling signal of each bit of the shift register is output between the shift register and the sample hold circuit. Delay time Data line drive device for an active type LCD panel, characterized in that a delay circuit with a delay on output to the sample-and-hold circuit. 2. The delay circuit according to claim 1, wherein a sampling signal of each bit of the shift register is input to one input terminal and an even number of these sampling signals are connected in series to the other input terminal. Active-type L, each of which is input through an inverter and whose output terminal is composed of an AND gate of each bit connected to each bit of the sample hold circuit.
A drive device for the data line of a CD panel. 3. The device according to claim 1, wherein the delay circuit outputs a sampling signal of each bit of the shift register,
And a control signal which falls at the same time as the clock signal and rises after a delay time of the output of the sampling signal is exceeded, and an AND circuit is provided for outputting to each bit of the sample hold circuit. Drive device for data line of active LCD panel. 4. The active type L according to claim 3, wherein the control signal comprises a clock signal.
A drive device for the data line of a CD panel.