JPS6384134A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To delete a matching error by providing a pattern which has a long side in an irradiating direction from the center of a semiconductor wafer and a sufficiently short side perpendicular to the long side symmetrically with respect to a radiation on a position detecting pattern region. CONSTITUTION:Position detecting pattern regions 17R, 17L and a rectangular pattern 18 in the region have long sides along the radiation from the center of all wafers 11 and a short side having a width (d) perpendicular thereto in such a manner that the long side size l >> d is set in the degree that a matching signal gain does not decrease at the time of matching. When the laser beam width is 10, d = 2mum, l=6mum are set. When a wafer having such a position detecting pattern is fed through a covering step having an azimuth from the center of the wafer by coating it with a photoresist, the absolute value of the apparent pattern position and the relative position displacement become substantially equal since the coverage characteristics to the patterns 18R, 18L are equal. Further, since the width (d) is small, the absolute and relative position displacements of the pattern are small. The regions 17U, 17L are similar, the apparent position displacement generated on the position detecting pattern is reduced to decrease the matching error in X-and Y-directions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) This invention relates to a semiconductor wafer provided with a position detection pattern for alignment.

(Prior art) Semiconductor integrated circuits are manufactured by coating photoresist on a semiconductor wafer, exposing and printing various patterns, and then performing a development process to form masks. It is manufactured by etching the underlying film and diffusing impurities.

Since exposure of various patterns is usually performed many times on one wafer, a positioning process called alignment is performed at the beginning of each exposure process.

FIG. 9 is a plan view of a conventional wafer on which a position detection pattern used in the alignment process is formed. In the figure, 11 is the wafer body, 12 is a notch called orientation flat, 11R% 13L, 1
3U are pattern areas for right position detection, left position detection, and upper position detection, respectively.

Several parallel rectangular patterns 14 are provided in each pattern area 13, and each rectangular pattern 14 is made of a silicon oxide film, polycrystalline silicon, aluminum, etc. on a wafer body 11 made of single crystal silicon. It is formed by leaving the In such a wafer, the right position detection pattern area 13R and the left position detection pattern area 13L are used to
alignment in the θ and θ directions, and alignment in the X direction using the upper position detection pattern area 13U.

The wafer body 11 is subjected to a photoresist coating process, a metal film sputtering process, etc. to this wafer.
If the process is carried out with orientation from the center of
As shown in the plan view of the figure, right position detection pattern area 1
Since the covering characteristics for the rectangular pattern 14R in 3R and the rectangular pattern L4L in the left position detection pattern area 13L are different, the appearance is absolute and relative to the upper pattern as shown by the broken line in the figure. Misalignment occurs.

In addition, in FIG. 10, the dimension a is the rectangular pattern 14.
The apparent size of L is the absolute displacement amount above, the apparent size of the rectangular pattern 14R is the absolute displacement amount above, C is the distance between both patterns 14L and L4R,
Furthermore, a-b is the relative positional shift amount between both patterns 14L114R.

Such positional deviation appears as a shift (parallel movement amount) and rotation (rotation amount) during alignment of the wafer body 11. For this reason, not only does the position of the semiconductor chips formed on the wafer body 11 shift overall, but also the variation increases due to rotation, and as a result, positional deviation occurs during alignment, reducing the yield of good chips. The disadvantage is that it decreases. For example, if a rotation of 10 ppm occurs, the diameter will be 5
If the shift at the center of an inch wafer is assumed to be 0, the positional deviation of the chips will occur by as much as 0.5 μm around the wafer. For this reason, even if the yield at the center of the wafer body 11 is increased, it is inevitable that the yield at the periphery of the wafer body 11 will decrease.

FIG. 11 is a plan view showing a conventional wafer different from the above. In this wafer, only a right position detection pattern area 13R and a left position detection pattern area 13L are provided, and each is provided with cross-shaped patterns 18R and L6L. After performing a process with orientation from the center of the wafer body, such as a photoresist coating process or a metal film sputtering process, on this wafer, as shown in the plan view of Fig. 12, The covering characteristics of the cross-shaped pattern 16R of the position detection pattern area 13R and the cross-shaped pattern IBL of the left position detection pattern area 13L in the wafer center direction are stronger due to their pattern shapes, so that A large pattern misalignment occurs. This positional deviation causes a particularly strong shift when aligning the wafer body 11. Therefore, the position of the chips formed on the wafer is largely shifted due to the shift.

At the same time as the positional shift due to the pattern process described above,
Pattern dimensions are also an important alignment factor. However, with patterns formed on conventional wafers, the apparent upper pattern width changes when the process is changed, so it also has the disadvantage that it is difficult to determine the mask dimensions to obtain the optimal finished pattern width. It's matching.

(Problems to be Solved by the Invention) As described above, in conventional wafers, apparent positional deviations tend to occur in the position detection patterns during the manufacturing process, which increases alignment errors. be. Furthermore, if the manufacturing process is different, the amount of positional deviation also changes, which makes it difficult to determine the mask dimensions for obtaining the optimal finished pattern width.

This invention was made in consideration of the above circumstances, and its purpose is to reduce the apparent positional deviation that occurs in the position detection pattern, thereby reducing alignment errors. Moreover, it is an object of the present invention to provide a semiconductor wafer in which the amount of positional deviation can be kept almost constant even if the manufacturing process is different, and thereby it is easy to determine the mask dimensions for obtaining the optimum finished pattern width.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor wafer of the present invention is a semiconductor wafer in which pattern areas for position detection are provided at a plurality of locations, and each pattern area has a pattern area from the center of the wafer. It has a long side along the radial direction, is symmetrical about the axis in the radial direction, and has a width in a direction perpendicular to the radial direction that is sufficiently smaller than the long side. At least one position detection pattern is provided.

(Function) In the semiconductor wafer of the present invention, the position detection pattern has a long side along the radiation direction from the center of the wafer,
By making the shape symmetrical with respect to the axis of the radiation direction, the apparent amount of upper positional deviation that occurs in each pattern after going through the process with orientation from the center of the wafer is equalized, and each pattern is By making the width in the direction perpendicular to the radial direction from the center of the wafer sufficiently smaller than the long side, the appearance of each pattern after going through the process with orientation from the center of the wafer can be improved. The amount of positional deviation is minimized.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a wafer according to an embodiment of the present invention. In the figure, 11 is a wafer body made of single crystal silicon, 12 is a notch called an orientation red flat, and 17R, 17L, and 17U are pattern areas for right position detection, left position detection, and upper position detection, respectively. be. Each of the pattern areas 17 is provided with several parallel rectangular patterns 18, respectively. Each rectangular pattern 18 is formed by selectively leaving a silicon oxide film, polycrystalline silicon, aluminum, or the like on the wafer body 11, as in the prior art.

In the wafer of this embodiment, the rectangular patterns 18 in the right position detection pattern area 17R, left position detection pattern area 17L, and right position detection pattern area L7R are all arranged along the radial direction from the center of the wafer body 11. It has a long side, and the width d in the direction perpendicular to the radial direction is made sufficiently smaller than the length l of the long side so that the gain of the alignment signal during alignment does not decrease. .

For example, the optimal pattern dimensions for rectangular pattern I8 are:
When the laser beam width is 10 μm, approximately d
is 2.0 μm, and e is 6.0 μm.

When a wafer having such a position detection pattern undergoes a coating process with orientation from the center of the wafer, such as a photoresist coating process or a metal film sputtering process, the pattern shown in Figure 2 is applied. As shown, since the covering characteristics for the rectangular pattern 18R of the right position detection pattern area 17R and the rectangular pattern 18L of the left position detection pattern area 17L are equal, the appearance indicated by the broken line in the figure is the same as that of the upper pattern position. Absolute and relative displacement occur approximately equally. Moreover, rectangular pattern 18R
Since the width d of and 18L is made as small as possible, the amount of absolute and relative positional deviation of the pattern position during the oriented coating process from the center of the wafer can be made extremely small. As a result, the apparent upper positional deviation that occurs in the position detection pattern can be reduced, which allows
Alignment errors in either direction of the Y direction can be reduced. This is the pattern area 17 for right position detection.
The alignment error when using the R rectangular pattern 18R and the rectangular pattern 18U of the upper position detection pattern area 17U can be similarly reduced.

Moreover, since the absolute amount of positional deviation of the pattern position can be made extremely small, the amount of positional deviation can be kept almost constant even if the manufacturing process is different. The dimensions can be easily determined.

Next, the alignment of the wafer body provided with the position detection pattern as described above will be explained. When aligning the wafer body using a laser beam, as shown in the perspective view of FIG. 3, the surface of the wafer body 11 to be aligned is irradiated with a laser beam, , each pattern area 17R, 17L, 17U for left position detection and upper position detection
The diffracted scattered light in each is detected by detectors 2OR, 2QL,
20U, and the center of each pattern area 17 is determined from these detection signals.

FIG. 4 is a side view showing the specific configuration of each of the detectors 2OR and 20L. The detectors 2QR and 2QL each include an objective lens 21 and a spectroscopic slit 22 installed at positions corresponding to each position detection pattern area of the wafer body 11, and are arranged at positions as shown by arrows in FIG. It is composed of a pair of detectors 23 that detect the light that has passed through the spectroscopic slit 22. Note that the wafer body 11 is placed on a wafer stage 24 that moves the wafer body 11 in the X and Y directions.

Figures 6 and 7 show alignment errors and their occurrence when alignment is performed using the conventional wafers shown in Figures 9 and 11, respectively, and Figure 8 shows alignment errors that occur when alignment is performed using the wafer of the present invention. It is a characteristic diagram showing frequency.

When detecting the center position of the wafer body 11 using the conventional wafer shown in FIG. (
radian) rotation occurs. When alignment is performed using such a wafer, both the shift and the amount of variation become large, as shown in the characteristic diagram of FIG.

Further, when the conventional wafer shown in FIG. 11 is used, no rotation occurs, but an extreme shift occurs.

Therefore, as shown in the characteristic diagram of FIG. 7, the shift becomes large.

On the other hand, when the wafer of this invention is used, both the rotation and shift can be kept low, so the 8th
As shown in the characteristic diagram in the figure, both the shift and the amount of variation become small.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, the pattern areas 17R, 17L, and 17U for right position detection, left position detection, and upper position detection are each provided with a plurality of rectangular patterns arranged in parallel. This is applied when alignment is performed by detecting diffracted and scattered light using a laser beam, and when alignment is performed by other methods, such as image processing, it is used for right position detection, left position detection, and upper position detection. Pattern area 17R for
, , 17L, and 17U may each have only one rectangular pattern.

[Effects of the Invention] As explained above, according to the present invention, it is possible to reduce the apparent upper positional deviation that occurs in the position detection pattern, thereby reducing alignment errors, and in addition, it is possible to reduce the alignment error. The amount of positional deviation can be kept almost constant even when the pattern is finished, thereby making it possible to provide a semiconductor wafer in which mask dimensions can be easily determined in order to obtain an optimal finished pattern width.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor wafer according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the positional deviation that occurs when the wafer of the above embodiment is used, and FIGS. 3 to 5 are 3 is a perspective view, FIG. 4 is a side view, FIG. 5 is a plan view, and FIGS. 6 to 8 are for explaining alignment using a wafer of the present invention. 9 is a plan view of a conventional wafer. FIG. 10 is a diagram illustrating positional deviation that occurs when the conventional wafer shown in FIG. 9 is used.
Figure 1 is a plan view of a conventional wafer different from the above;
This figure is a diagram for explaining the positional deviation that occurs when the conventional wafer shown in FIG. 11 is used. 11... Wafer body, 12... Notch, 15...
- Center point, 17... Pattern area for position detection, 18.
...Rectangular pattern.

Claims (2)

[Claims] (1) In a semiconductor wafer in which pattern areas for position detection are provided at multiple locations, each pattern area has a long side along the radial direction from the center of the wafer, and 1. A semiconductor wafer comprising at least one position detection pattern that is symmetrical in shape and whose width in a direction perpendicular to the radiation direction is sufficiently smaller than the long side. (2) The semiconductor wafer according to claim 1, wherein each of the position detection pattern areas is provided with a plurality of position detection patterns arranged in parallel.