JPS6384190U - - Google Patents

Description

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, and FIG.
Fig. 2 is a schematic diagram of the RAM card socket, Fig. 3 is an overall circuit diagram, Fig. 4 is a plan view showing the main parts of the switch panel of the keyboard shown in Fig. 3, and Fig. 5 is a plan view of the external appearance of the M card. The figure shows the memory format of the RAM card, Figure 6 is a diagram specifically showing the model name code of Figure 5, and Figure 7 is the RO of Figure 5.
A diagram specifically representing the code indicating whether it is M or RAM,
Figure 8 is a diagram specifically showing the memory capacity code in Figure 5, Figure 9 is a diagram specifically representing the header of the first rhythm pattern in Figure 5, and Figure 10 is a diagram specifically showing the header of the first rhythm pattern in Figure 5. Figure 11 is a diagram specifically representing the header of the first tone data, Figure 11 is a diagram concretely representing the header of the sequence data in Figure 5, and Figure 12 is a diagram specifically representing the data format of the rhythm pattern data in Figure 5. Figure 13 is a diagram showing the data format of the tone data in Figure 5, and Figure 14 is a diagram showing the data format of the tone data in Figure 5.
15 is a diagram showing the main flowchart for explaining the overall operation, and FIG. 16 is a diagram showing the data format of the sequence data in the figure.
FIG. 17 is a flowchart explaining the details of step S2 in FIG.
Figure 1 showing a flowchart explaining details of
8 is a diagram showing a flowchart explaining details of step S5 in FIG. 15, FIG. 19 is a diagram showing a flowchart explaining details of step S9 in FIG. 15, and FIG. 20 is a diagram showing a flowchart explaining details of step S9 in FIG. Diagram 21 showing a flowchart explaining details of S10
The figure shows the details of the sequence memory playback mode processing in step S10-2 in FIG.
FIG. 22 is a diagram showing details of the sequence memory playback mode processing in step S10-2 of FIG. 20. 1...RAM card (external memory device), 2...
...RAM card socket, 30...Melody sound source circuit, 40...Accompaniment sound source circuit, 50...Rhythm sound source circuit, 60...Keyboard, 60-1 to 60
-4...Tone select switch, 60-5...
External tone specification switch, 60-6 to 60-9...
...Rhythm select switch, 60-10...External rhythm specification switch, 60-11...Sequence memory mode switch, 60-12...External sequence memory specification switch, 60-13...Light mode switch, 60-14... Start/stop switch, 70...ROM, 80...RA
M (internal memory), 100...CPU.

Claims (1)

[Claims for Utility Model Registration] (1) The electronic musical instrument has a memory device that is electrically connected to the body of the electronic musical instrument, and the memory device is capable of storing multiple types of information for playing the musical instrument. A memory control device for an electronic musical instrument, characterized in that a main body is configured to directly access the memory device. (2) The above-mentioned memory device is a semiconductor memory card, and the above-mentioned electronic device main body is capable of reading/writing the above-mentioned plurality of types of information with respect to the semiconductor memory card. A memory control device for an electronic musical instrument according to item 1. (3) Utility model registration claim 1, characterized in that the memory device is capable of reading/writing each of the plurality of types of information separately and independently.
A memory control device for an electronic musical instrument as described in 2.