JPS6384191U - - Google Patents

Info

Publication number
JPS6384191U
JPS6384191U JP17951586U JP17951586U JPS6384191U JP S6384191 U JPS6384191 U JP S6384191U JP 17951586 U JP17951586 U JP 17951586U JP 17951586 U JP17951586 U JP 17951586U JP S6384191 U JPS6384191 U JP S6384191U
Authority
JP
Japan
Prior art keywords
musical instrument
performance
electronic musical
external memory
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17951586U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17951586U priority Critical patent/JPS6384191U/ja
Publication of JPS6384191U publication Critical patent/JPS6384191U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案の一実施例を示し、第1図はRA
Mカードの外観平面図、第2図はRAMカード用
ソケツトの概略図、第3図は全体回路構成図、第
4図は第3図のキーボードのスイツチパネルの要
部を示す平面図、第5図はRAMカードのメモリ
フオーマツトを示す図、第6図は第5図の機種名
コードを具体的に示す図、第7図は第5図のRO
MかRAMかを示すコードを具体的に表わす図、
第8図は第5図のメモリー容量のコードを具体的
に示す図、第9図は第5図の第1番目のリズムパ
ターンのヘツダーを具体的に表わす図、第10図
は第5図の第1番目の音色データのヘツダーを具
体的に表わす図、第11図は第5図のシーケンス
データのヘツダーを具体的に表わす図、第12図
は第5図のリズムパターンデータのデータフオー
マツトを示す図、第13図は第5図の音色データ
のデータフオーマツトを示す図、第14図は第5
図のシーケンスデータのデータフオーマツトを示
す図、第15図は全体の動作を説明するためのメ
インフローチヤートを示す図、第16図は第15
図のステツプS2の詳細を説明するフローチヤー
トを示す図、第17図は第15図のステツプS3
の詳細を説明するフローチヤートを示す図、第1
8図は第15図のステツプS5の詳細を説明する
フローチヤートを示す図、第19図は第15図の
ステツプS9の詳細を説明するフローチヤートを
示す図、第20図は第15図のステツプS10の
詳細を説明するフローチヤートを示す図、第21
図は第20図のステツプS10―2のシーケンス
メモリの再生のモードの処理の詳細を示す図、
第22図は第20図のステツプS10―2のシー
ケンスメモリの再生のモードの処理の詳細を示
す図である。 1……RAMカード(外部メモリ装置)、2…
…RAMカード用ソケツト、30……メロデイ音
源回路、40……伴奏音源回路、50……リズム
音源回路、60……キーボード、60―1〜60
―4……トーンセレクトスイツチ、60―5……
外部トーン指定スイツチ、60―6〜60―9…
…リズムセレクトスイツチ、60―10……外部
リズム指定スイツチ、60―11……シーケンス
メモリモードスイツチ、60―12……外部シー
ケンスメモリ指定スイツチ、60―13……ライ
トモードスイツチ、60―14……スタート/ス
トツプスイツチ、70……ROM、80……RA
M(内部メモリ)、100……CPU。
The drawings show an embodiment of the present invention, and FIG.
Fig. 2 is a schematic diagram of the RAM card socket, Fig. 3 is an overall circuit diagram, Fig. 4 is a plan view showing the main parts of the switch panel of the keyboard shown in Fig. 3, and Fig. 5 is a plan view of the external appearance of the M card. The figure shows the memory format of the RAM card, Figure 6 is a diagram specifically showing the model name code of Figure 5, and Figure 7 is the RO of Figure 5.
A diagram specifically representing the code indicating whether it is M or RAM,
Figure 8 is a diagram specifically showing the memory capacity code in Figure 5, Figure 9 is a diagram specifically representing the header of the first rhythm pattern in Figure 5, and Figure 10 is a diagram specifically showing the header of the first rhythm pattern in Figure 5. Figure 11 is a diagram specifically representing the header of the first tone data, Figure 11 is a diagram concretely representing the header of the sequence data in Figure 5, and Figure 12 is a diagram specifically representing the data format of the rhythm pattern data in Figure 5. Figure 13 is a diagram showing the data format of the tone data in Figure 5, and Figure 14 is a diagram showing the data format of the tone data in Figure 5.
15 is a diagram showing the main flowchart for explaining the overall operation, and FIG. 16 is a diagram showing the data format of the sequence data in the figure.
FIG. 17 is a flowchart explaining the details of step S2 in FIG.
Figure 1 showing a flowchart explaining details of
8 is a diagram showing a flowchart explaining details of step S5 in FIG. 15, FIG. 19 is a diagram showing a flowchart explaining details of step S9 in FIG. 15, and FIG. 20 is a diagram showing a flowchart explaining details of step S9 in FIG. Diagram 21 showing a flowchart explaining details of S10
The figure shows the details of the sequence memory playback mode processing in step S10-2 in FIG.
FIG. 22 is a diagram showing details of the sequence memory playback mode processing in step S10-2 of FIG. 20. 1...RAM card (external memory device), 2...
...RAM card socket, 30...Melody sound source circuit, 40...Accompaniment sound source circuit, 50...Rhythm sound source circuit, 60...Keyboard, 60-1 to 60
-4...Tone select switch, 60-5...
External tone specification switch, 60-6 to 60-9...
...Rhythm select switch, 60-10...External rhythm specification switch, 60-11...Sequence memory mode switch, 60-12...External sequence memory specification switch, 60-13...Light mode switch, 60-14... Start/stop switch, 70...ROM, 80...RA
M (internal memory), 100...CPU.

Claims (1)

【実用新案登録請求の範囲】 (1) 電子楽器本体に電気的に接続される外部メ
モリ装置を有し、この外部メモリ装置は電子楽器
本体が直接アクセス可能となつており、この外部
メモリ装置が電子楽器本体からアクセスされてい
るときに、電気的接続が解除されると、電子楽器
本体内部に設けられた内部メモリを使用して演奏
制御をするよう切換える制御手段を有することを
特徴とする電子楽器の演奏制御装置。 (2) 上記外部メモリ装置がアクセスされている
ときに、自動リズム演奏がなされており、しかも
その途中で上記電気的接続が解除されたことが検
知されると、上記制御手段は上記自動リズム演奏
を中止した後、上記内部メモリを使用して演奏制
御をするよう切換えるようにしたことを特徴とす
る実用新案登録請求の範囲第1項記載の電子楽器
の演奏制御装置。 (3) 上記外部メモリ装置は、半導体メモリカー
ドであり、上記電子楽器本体は、この半導体メモ
リカードに対して楽器演奏のための複数種類の情
報を直接アクセスできるようにしたことを特徴と
する実用新案登録請求の範囲第1項記載の電子楽
器の演奏制御装置。
[Claims for Utility Model Registration] (1) It has an external memory device that is electrically connected to the main body of the electronic musical instrument, and this external memory device can be directly accessed by the main body of the electronic musical instrument, and this external memory device is An electronic musical instrument characterized by having a control means that switches to perform performance control using an internal memory provided inside the electronic musical instrument body when the electrical connection is released while the electronic musical instrument is being accessed from the musical instrument body. performance control device. (2) If it is detected that the automatic rhythm performance is being performed while the external memory device is being accessed, and that the electrical connection is disconnected midway through, the control means will cause the automatic rhythm performance to be performed. 2. The performance control device for an electronic musical instrument according to claim 1, wherein after stopping the performance, the internal memory is used to control the performance. (3) A utility model characterized in that the external memory device is a semiconductor memory card, and the electronic musical instrument main body can directly access multiple types of information for musical instrument performance to the semiconductor memory card. A performance control device for an electronic musical instrument according to claim 1.
JP17951586U 1986-11-21 1986-11-21 Pending JPS6384191U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17951586U JPS6384191U (en) 1986-11-21 1986-11-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17951586U JPS6384191U (en) 1986-11-21 1986-11-21

Publications (1)

Publication Number Publication Date
JPS6384191U true JPS6384191U (en) 1988-06-02

Family

ID=31122644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17951586U Pending JPS6384191U (en) 1986-11-21 1986-11-21

Country Status (1)

Country Link
JP (1) JPS6384191U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60193189A (en) * 1984-03-15 1985-10-01 Canon Inc Electrical and electronic equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60193189A (en) * 1984-03-15 1985-10-01 Canon Inc Electrical and electronic equipment

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