JPS6385599A - Color image display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a color image display device using square liquid crystals, etc., and particularly to a column direction drive circuit thereof. The general arrangement of color pixels in display devices is as shown in Figure 3 ((1) and (6)). Here, R represents red, G represents green, and B represents blue color pixels. In Figure 3 (α), pixels of the same color are arranged in the vertical direction, and R, G, and B color pixels are arranged alternately in the horizontal direction. However, with this arrangement of color pixels, the resolution in the vertical direction is inferior. .In Fig. 3(b), there are R in both the vertical and horizontal directions.
G and B color pixels are alternately arranged in parallel to solve the problem in FIG. 3 (α). However, with this arrangement of color pixels, the resolution in the diagonal direction (diagonally downward to the left in FIG. 3(b)) is poor.

In order to compensate for the drawbacks in image display due to the conventional color pixel arrangement as described above, a color image display device having a color pixel arrangement as shown in FIG. 4 has been proposed.
The pixels are shifted in each row, and R, G, and B color pixels are arranged alternately in the horizontal direction, so that single-color pixels are not continuous in any of the vertical, horizontal, and diagonal directions. In FIG. 4, the shift between the j-th row and the j+1-th row is 1/2 pixel.0 [Problem to be solved by the invention] Regarding conventional column direction driving of a color image display device of color pixels as shown in FIG. explain. In the column direction, video data is output from the drive circuit as a drive signal, 501 in FIG.
is a video signal using a television as an example. Since the video signal of the j-th (H: horizontal synchronization signal period) and the (j+1) u-th video signal are close to each other, they are generally almost the same video data. 502 is an enlarged part of 501. Reference numeral 503 denotes a sampling clock signal for sampling video data, whose period is the same as the time corresponding to one pixel.O sampling is performed at the falling edge of the sampling clock. In the j-th row, the video data of A of the 1H-th video signal is written to the pixel α, and the video data of C is written to the pixel C. Therefore, in the (j+1)th row, the (j+
1) The H-th video data B, D, and D should always be written at the sampling clock 50.
Since the video data is sampled at the falling edge of 5, video data A, O are written to each pixel of A and D. This reduces the horizontal resolution of the image.

In view of the problems of the prior art as described above, the present invention provides the fourth aspect of the present invention.
The purpose of the present invention is to increase the resolution in the horizontal direction in a color image display device in which color pixels are arranged as shown in the figure. ) a first row in which pixels of each color are arranged alternately in the horizontal direction, and b) a second row in which pixels of each color are arranged alternately in the horizontal direction, shifted by 2 pixels (z<1) from the first row. C) a column-direction drive circuit that samples the video signal in a time-division manner and generates a column-direction drive signal for the color image display; d) The timing of sampling the video signal corresponding to the first row and the timing of sampling the video signal corresponding to the second row are xt (t is the time corresponding to one pixel in the horizontal direction) A color image display device is proposed, characterized in that it has sampling means that are out of phase by an amount of

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

(First Embodiment) FIG. 1 is a block diagram of the configuration of a first embodiment of the present invention, and FIG. 6 is a time chart thereof.

101 is a red (R) image data sampling circuit O
n circuit A/D converter 104 and encoder 1
07 Yog) oA/D controller/ku part 104 is further 0
Consists of 6. Comparator 105 has two inputs,
An R signal is connected to one side, and one tap terminal of a group of resistors connected in series so as to generate voltages corresponding to the desired number of gradations is connected to the other side. Comparator 105 compares both inputs, determines the level of the R signal, and outputs a digital signal. sampling switch 10
6 converts the A/D converted digital signal to 11
Sampling is performed using the output signal of EX-NOR gate No. 1. The timing changes at the rising edge of the 111 signal as shown in FIG. The A/D converter 104 is provided with a desired number of gradations, for example, in the case of 16 gradations, there are 16 A/D converters 104.
The outputs are input to an encoder 107 and encoded into a 4-bit code. The green (G) III image data sampling circuit 102 and the blue (B) image data sampling circuit 103 also have the same configuration as 101.

The 4-bit digitized R, G, B image take 108 is input to a multiplexer 109. In the multiplexer 109, the horizontal direction of the color image display body,
The image data 108 is multiplexed in accordance with the arrangement of color pixels in the vertical direction, and 4-bit image data 117 is output to the first memory group 114.

A shift register 113 transfers shift data D using a shift clock φ.

114 is a first memory group, each memory having:
For example, it consists of a 4-bit latch (4 bits)
It is configured to take in image data 117. Image data is taken in by the output 11B of each stage of the shift register 115 ◇Each memory of the second memory group 115 also
For example, it is composed of a 4-bit latch, and is configured to take in the 4-bit "a>output 119" of the corresponding memory of the first memory group. This is done by the LOAD signal generated after the loading of the data is completed.

The 4-bit image data 120 taken in by the LOAD signal is output to the driver 116.
6, the 4-bit image data 120 is used to set the ON potentials VoN and OPI” supplied from the outside to V 077%.
Determine the ratio in the selection period of column direction drive signal 1
21, output to a color image display.

110 is a toggle p/IF (flip flop), and a signal is input as a toggle signal. D is also a shift data signal for the shift register 113. D is a short pulse with a period of 1H as shown in FIG.
a L OA close to the start position of image information in H
The D signal slightly precedes the D signal. The Q output of the toggle F/IF 110 is a signal obtained by dividing D, and repeats 1J I rOJ every 1H. OL is a clock signal, and 0111, whose period corresponds to the time of one pixel, is EX - It is a NOR gate, and inputs the CL signal and the 110Q output signal. Therefore, 11
The output of 1 is the same phase of the OL times the signal every 1H as shown in Figure 6.
, the reverse phase will be repeated. Since each R, G, and B sampling circuit uses the signal 111 as a sampling signal, the 4-bit image data 1 from the multiplexer 109
17 is 0 in the order of A and O of the video signal in the jH-th image data, and image data 117 is taken into the first memory group 114 as an output 118 of each stage of the shift register 113. At the j-l-IH, the 4-bit image data 117 is in the order of B and D of the video signal, and is taken into the first memory group 114 as an output 118 of each stage of the shift register 113.

As a result, the pixels α and C in row j of FIG.
D is written and the resolution in the horizontal direction can be increased.

(Second Embodiment) Fig. 2 is a block diagram of the configuration of the second embodiment of the present invention. Fig. 7 is its timing chart. 0203, which is an IN, is a multiplexer for R, G, and B. The name of each color is entered. At 203, image data is multiplexed in accordance with the arrangement of color pixels in the horizontal and vertical directions of the color image display body.204 is a shift register which transfers shift data D using a shift clock φ. 2
05 is a sampling hold circuit. The second stage is composed of an analog switch 206, a capacitor fIk 207, and a buffer amplifier 208. analog switch 206
The control signal 210 is transmitted from each stage of the shift register 204 to two
10, and the negative end is the multiplexer 20.
3 is connected to the image data line from 3, and the other end is connected to the capacitor 207 (
One end of which is grounded) and the output of 0208 connected to the buffer amplifier 208 is the column direction drive signal 211.
It is. To explain its operation, the shift register 204
At the output 210 of each stage, the analog switch 206 is turned on.
Then, the image data at that time is written to the capacity 207. Based on the image data written to the capacitor 207, the buffer amplifier 20 forms a column direction drive signal 211. ◇ 201 is a toggle F/'F to which a signal is input as a toggle signal. D is also a shift data signal for the shift register 204. As shown in FIG. 7, D is a short pulse of 1H period, and is close to the start position of image information in 1H. Toggle y/IF 201 Q output 209
is a signal obtained by dividing the frequency of D, and it is "1" and "0" every 1H.
"repeat. OIi is a clock signal whose period corresponds to the time of one pixel. 202 is ICX-NOR
gate, the CIl signal and the Q output signal 209 of 201
is being entered. The output of 202 is the shift register 204
◇Therefore, 204φ repeats the in-phase and anti-phase with respect to the CL multiplied signal every 1H as shown in FIG. In the shift register 204, shift data D is transferred at the falling edge of the shift clock φ. Therefore, at the jH, image data is sampled in the order of A and O of the video signal, and at the j+IH, image data is sampled in the order of E and D.

As a result, video data A and O are written into pixels α and C in row j of Figure 4, and the same <B and D are written into pixels α and d in row j+1, increasing the resolution in the horizontal direction. [Effects of the Invention] As explained above, according to the present invention, - in a column direction drive circuit of a color image display body having a pixel shift of one pixel or less for each row, By shifting the sampling timing of the video signal in each row by the time corresponding to the pixel shift, a color image display device that does not impair the horizontal resolution can be provided.In the present invention, the pixel shift in each row is Although the explanation has been made for 1/2 pixel, it is clear that the color image display device according to the present invention can be realized with the same configuration even with other deviations of 1 pixel or less.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1: A block diagram of a first embodiment of the present invention; Fig. 2: A block diagram of a second embodiment of the present invention; Fig. 5 (α); (b)...Color pixel arrangement diagram in a color image display body Fig. 4...Color pixel arrangement diagram in a color image display body which is a premise of the present invention Fig. 5...Conventional video signal sampling Time chart figure 6...Time chart figure 7 of the first figure number section...
・Recovery of the time chart of the second answering section Applicant Seiko Epson Corporation Figure 4 Figure 5

Claims (1)

[Claims] a) A first row in which pixels of each color are arranged alternately in the horizontal direction, and b) pixels of each color are arranged alternately in the horizontal direction, shifted by x pixels (x<1) with respect to the first row. c) sampling the video signal in a time-division manner, and driving a column-direction drive signal of the color image display; d) The timing of sampling the video signal corresponding to the first row and the timing of sampling the video signal corresponding to the second row are xt (t is in the horizontal direction). 1. A color image display device comprising sampling means whose phase is shifted by a time corresponding to one pixel.