JPS6385923U - - Google Patents
Info
- Publication number
- JPS6385923U JPS6385923U JP18149486U JP18149486U JPS6385923U JP S6385923 U JPS6385923 U JP S6385923U JP 18149486 U JP18149486 U JP 18149486U JP 18149486 U JP18149486 U JP 18149486U JP S6385923 U JPS6385923 U JP S6385923U
- Authority
- JP
- Japan
- Prior art keywords
- constant current
- current source
- connection
- transistor
- connection point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
Description
第1図は本考案の一実施例を示す構成図、第2
図はその説明のための図、第3図は従来例の構成
図、第4図及び第5図はその説明のための図であ
る。
1及び4はオフセツトキヤンセル用のトランジ
スタ、2,5及び21は定電流源、3,6及び9
はスイツチング素子を構成するトランジスタ、1
0は入力端子、11は出力端子である。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a diagram for explaining the same, FIG. 3 is a configuration diagram of a conventional example, and FIGS. 4 and 5 are diagrams for explaining the same. 1 and 4 are transistors for offset cancelling, 2, 5 and 21 are constant current sources, 3, 6 and 9
is a transistor constituting a switching element, 1
0 is an input terminal, and 11 is an output terminal.
Claims (1)
、ダイオード、上記第1の定電流源と同じ電流値
の第2の定電流源及び第1の接続スイツチの直列
回路が接続され、 上記第1及び第2の電源端子の間にトランジス
タのコレクタ・エミツタ、第3の定電流源及び第
2の接続スイツチの直列回路が接続され、 上記第1の定電流源及びダイオードの接続点は
、上記トランジスタのベースに接続されると共に
、その接続点は第3の接続スイツチを介して上記
第2の電源端子に接続され、 上記ダイオード及び第2の定電流源の接続点よ
り入力端子が導出されると共に、上記トランジス
タ及び第3の定電流源の接続点より出力端子が導
出され、 上記第1及び第2の接続スイツチと上記第3の
接続スイツチとは互いに位相反転されたゲートパ
ルスでオン・オフ制御されることを特徴とするス
イツチ回路。[Claims for Utility Model Registration] A first constant current source, a diode, a second constant current source with the same current value as the first constant current source, and a first constant current source connected between the first and second power supply terminals. A series circuit of the connection switch is connected, a series circuit of the collector-emitter of the transistor, a third constant current source, and a second connection switch is connected between the first and second power supply terminals, and a series circuit of the first and second connection switches is connected. A connection point between the constant current source and the diode is connected to the base of the transistor, and the connection point is connected to the second power supply terminal via a third connection switch, and the connection point between the constant current source and the second constant current source is connected to the base of the transistor. An input terminal is led out from the connection point of the source, and an output terminal is led out from the connection point of the transistor and the third constant current source, and the first and second connection switches and the third connection switch are A switch circuit characterized by being on/off controlled by gate pulses whose phases are reversed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18149486U JPS6385923U (en) | 1986-11-26 | 1986-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18149486U JPS6385923U (en) | 1986-11-26 | 1986-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6385923U true JPS6385923U (en) | 1988-06-04 |
Family
ID=31126414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18149486U Pending JPS6385923U (en) | 1986-11-26 | 1986-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6385923U (en) |
-
1986
- 1986-11-26 JP JP18149486U patent/JPS6385923U/ja active Pending
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