JPS6323733U - - Google Patents
Info
- Publication number
- JPS6323733U JPS6323733U JP11618186U JP11618186U JPS6323733U JP S6323733 U JPS6323733 U JP S6323733U JP 11618186 U JP11618186 U JP 11618186U JP 11618186 U JP11618186 U JP 11618186U JP S6323733 U JPS6323733 U JP S6323733U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- data holding
- push
- output transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 1
Landscapes
- Keying Circuit Devices (AREA)
Description
第１図は本考案に係る電源開閉回路の一実施例
を示す回路図、第２図は従来例を示す回路図であ
る。
１……プツシユ・オン・スイツチ、２……デー
タ保持回路、ＣＰ……保持指令端子、Ｄ……デー
タ入力端子、Ｑ……データ出力端子、３……出力
トランジスタ、４……微分回路、５……駆動トラ
ンジスタ、６……定電圧回路、ＺＤ……ゼナーダ
イオード。
FIG. 1 is a circuit diagram showing an embodiment of the power switching circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1... Push-on switch, 2... Data holding circuit, CP... Holding command terminal, D... Data input terminal, Q... Data output terminal, 3... Output transistor, 4... Differential circuit, 5 ...Drive transistor, 6... Constant voltage circuit, ZD... Zener diode.
Claims (1)
ク機構を持たないプツシユ・オン・スイツチとか
ら成る電源開閉回路において、前記データ保持回
路は前記出力トランジスタの出力をデータ入力と
し、前記プツシユ・オン・スイツチは微分回路を
介して前記データ保持回路に入力されていること
を特徴とする電源開閉回路。 (2) 前記出力トランジスタには定電圧回路を介
する駆動トランジスタがベースに接続されて定電
圧出力とされていることを特徴とする実用新案登
録請求の範囲(1)項記載の電源開閉回路。[Claims for Utility Model Registration] (1) In a power switching circuit consisting of a data holding circuit, an output transistor, and a push-on switch without a locking mechanism, the data holding circuit uses the output of the output transistor as a data input. , wherein the push-on switch is input to the data holding circuit via a differential circuit. (2) The power switching circuit according to claim (1), which is a registered utility model, characterized in that a drive transistor is connected to the base of the output transistor via a constant voltage circuit to output a constant voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11618186U JPS6323733U (en) | 1986-07-29 | 1986-07-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11618186U JPS6323733U (en) | 1986-07-29 | 1986-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6323733U true JPS6323733U (en) | 1988-02-17 |
Family
ID=31000531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11618186U Pending JPS6323733U (en) | 1986-07-29 | 1986-07-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6323733U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5746417A (en) * | 1980-09-04 | 1982-03-16 | Matsushita Electric Industrial Co Ltd | Erroneous operation preventing device |
-
1986
- 1986-07-29 JP JP11618186U patent/JPS6323733U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5746417A (en) * | 1980-09-04 | 1982-03-16 | Matsushita Electric Industrial Co Ltd | Erroneous operation preventing device |
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