JPS6386065A - Synchronizing system for multi-processor system - Google Patents

Abstract

PURPOSE:To surely secure the rise synchronism of a multi-processor system by providing a flag showing whether the initial information on a subprocessor is set or not and checking said flag via a main processor. CONSTITUTION:The set and unset states of the initial information on a subprocessor 2 are stored in a flip-flop 7 when the system initial processing is carried out in an application and reset modes of a power supply. A flag showing the state of the flip-flop 7, i.e., the set or unset state of the initial information on the processor 2 is set to a bit 7 of an 8-bit I/O memory 8. The memory 8 is connected to a main processor 1 and the data on the bit 7 is fetched by the processor 1 to be checked. Thus the rise synchronism is attained between both processors 1 and 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization method for a multiprocessor system having a plurality of independent processors.

[Conventional technology]

A multiprocessor is a computer system that has multiple independent processors (arithmetic units), and some storage devices and peripheral devices are shared between each processor, thereby reducing the memory cost per processor and increasing the overall system efficiency. In addition to improving processing capacity, it has the feature that even if one processor goes down, it can be replaced by another processor, increasing the system's efficiency.

FIG. 5 shows a schematic configuration diagram of a conventional multiprocessor system, in which 1 is a main processor, 2 is a sub-processor, 3 is a reset circuit for each processor 1 and 2,
Each processor 1.2 is connected via a respective bus 4.5 to a shared two-boat memory 6, with both processors 1.
．． Data is exchanged between the two through a two-board memory 6.

The initial processing procedure of each processor in the multiprocessor system configured as described above will be explained based on the flowcharts shown in FIGS. 6 and 7.

When the multiprocessor system is powered on and reset, the processing program shown in FIG. set.

On the other hand, in the main processor 1, when the processing program shown in FIG. 7 starts in the initial processing at power-on and reset, first, step 50
, a process is performed in which the sub-processor 2 waits for sufficient time to set the initial information, and then
In step 51, the initial information set in the 2-port memory 6 is checked, and in the next step 52, it is determined whether the initial information is normal. Here, if it is determined to be normal, the process proceeds to step 53, where initial processing between the main processor 1 and the sub-processor 2 is performed. If the initial information is determined to be abnormal, the process proceeds to step 54, where it is determined that the sub-processor 2 is abnormal, and error processing such as stopping the system is performed.

[Problem that the invention seeks to solve]

In the startup synchronization method of the conventional multiprocessor system as described above, it is impossible to determine whether the subprocessor 2 has started up unless the main processor 1 checks the initial information of the subprocessor 2 set in the 2-port memory 6. . Therefore, if the previous data remains in the correct state on memory 6 at the time of reset,
There is a problem in that even if the sub-processor 2 is not operating, the main processor 1 is unable to determine an abnormality and treats the system as normal.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a synchronization method for a multiprocessor system that can reliably synchronize the start-up of multiprocessors without making a misjudgment. do.

[Means for solving problems]

The synchronization method of the multiprocessor system according to the present invention includes a flag setting means for indicating whether or not the initial information setting of the subprocessor has been completed, and a flag of the flag setting means is checked by the main processor to determine whether the subprocessor has started up or not. It is provided with a means for determining whether the

[For production]

In the present invention, when initial information is set in the shared memory during the initial processing at power-on and reset of the system, the initial information set completion and incomplete data of the sub-processor are set in the flag setting means, and this flag is set. By checking with the determination means on the main processor side, the start-up of the sub-processor is detected and the start-up of the system is synchronized. Therefore,
Reliable system synchronization is possible without the main processor making discrimination errors as in the past.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 shows a block diagram of a multiprocessor system synchronization method according to the present invention. In the figure, 1 is a main processor, 2 is a sub-processor, 3 is a reset circuit for these processors, and 6 is a shared two-boat memory connected to the main processor l and sub-processor 2 via buses 4 and 5, respectively. , these are similar to those shown in FIG.

Further, 7 is a flip-flop that stores the setting completion and setting incomplete states of the initial information of the sub-processor 2 during the initial processing of the system at power-on and reset, and its input terminal S is connected to the sub-processor 2. And the reset terminal R is connected to the above-mentioned reset circuit 3.
A reset circuit has been added. 8
is an 8-bit configuration I10 memory as shown in Figure 2,
Bit 7 is the output terminal Q of the flip-flop 7.
is connected, and a flag indicating the state of the flip-flop 7, that is, the state in which the initial information setting of the sub-processor 2 is completed or the setting is not completed, is set.

Note that the flag when the initial information set is completed is “l”.
”, and the flag when the set is incomplete is “0”. Also, the I10 memory 8 is connected to the main processor 1, and the data in bit 7 of the I10 memory 8 is taken into the main processor 1 and checked. By doing so, synchronization of the start-up of the main processor and the sub-processor 2 is realized.

Next, the initial processing operation of the multiprocessor system of this embodiment configured as described above will be explained with reference to the flowcharts of FIGS. 3 and 4.

Here, FIG. 3 is a flowchart showing the processing procedure of the sub-processor 2, and FIG. 4 is a flowchart showing the processing procedure of the main processor 1.

When the multiprocessor system is powered on or reset, the subprocessor 2 first starts the processing program shown in FIG.
Initial information required between the two ports is set in the two-port memory 6. Thereafter, in step 21, initial information set completion processing is executed and the result is output to the flip-flop 7. Here, if the initial information writing is completed, the set completion flag is set by setting the flip-flop 7, and if the initial information writing is not completed, the set incomplete flag is set by resetting the flip-flop 7. You will earn cents by doing so. As a result, when the set is completed, the output of the flip-flop 7 becomes "1", and when the set is not completed, the output of the flip-flop becomes 0", and these are stored in the T10 memory 8.
is stored in bit 7 of

On the other hand, on the main processor 1 side, when the processing program shown in FIG. 4 starts, first, in step 30,
A process is performed in which the sub-processor 2 waits for sufficient time to set the initial information, and then step 3
1, the data stored in the T10 memory 8 is read into the main processor 1. In the next step 32, it is determined whether or not the initial information writing has been completed, depending on whether the flag bit of the read storage data is 1'' or 0''. Here, if the flag = "1", that is, it is determined that the cent is completed, the process proceeds to step 33, where initial processing between the main processor 1 and the sub-processor 2 is performed, and both processors
, 2 are synchronized. Also, flag="O",
That is, when it is determined that the set is incomplete, the process proceeds to step 34, where it is assumed that the sub-processor 2 is abnormal and error processing such as system stop is executed.

Note that when the power is turned off or reset, the flip-flop 7 is reset, so its output becomes 0'' and T
Bit 7 of 10 memory 8 also becomes "0".

In this embodiment as described above, a flag is provided to indicate whether or not the initial information setting of the sub-processor has been completed.
The “1” and “0” states of this flag are
Since it is decided whether or not sub-processor 1 has started up by checking with This makes it possible to solve the problem that sub-processor 1 is unable to determine whether there is an abnormality in sub-processor 2, and it is also possible to reliably synchronize the start-up of the multi-processors.

Note that in the above embodiment, a system in which there is one main processor 1 and one sub-processor 2 is described;
Even if there are two or more sub-processors 2, it is possible to synchronize the start-up between each of these sub-processors and the main processor using the same method as in the above embodiment.

〔Effect of the invention〕

As described above, according to the present invention, in a multiprocessor system, a flag is provided to indicate whether or not writing of the initial information of a subprocessor has been completed, and by checking this flag in the main processor, it is possible to determine whether or not the subprocessor has started up. Since the initial processing is performed when the multiprocessor system starts up, it is possible to reliably synchronize the start-up of the multiprocessor system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a synchronization method of a multiprocessor system according to the present invention, FIG. 2 is a state diagram of the T10 memory in FIG. 1, and FIGS. 3 and 4 are system diagrams according to an embodiment of the invention. FIG. 5 is a block diagram of a conventional multiprocessor system, and FIGS. 6 and 7 are flowcharts showing the processing procedure of a conventional system. 1... Main processor, 2... Sub processor,
3... Reset circuit, 6... Shared memory, 7...
Flip-flop, 8...I10 memory. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] In a multiprocessor system having a main processor and sub-processors. A flag setting means for indicating whether initial information setting of the sub-processor has been completed, and a means for determining whether or not the sub-processor has started up by checking the flag of the flag setting means in the main processor are provided. Features a synchronization method for multiprocessor systems.