JPS638852A - Data transferring circuit - Google Patents

Abstract

PURPOSE:To shorten the time to monopolize a bus with one receiving circuit by holding the data sent from a transmitting circuit at the receiving circuit and sending response data to show the completion of the receiving to the transmitting circuit with the receiving circuit by holding the data. CONSTITUTION:When an instruction to a memory 2a is outputted to a time t1, the data on a bus 3 are fetched and held by a latching signal corresponding to the instruction data with a memory 2a. When the instruction to a memory 2b is outputted to the time t2, the memory 2b fetches and held the data on the bus 3 by the latching signal corresponding to the instruction data. At this time, the processing by the held data is continued for the memory 2a, and the data to ghe memory 2b can be sent in parallel on the bus 3. thus, since a latching circuit 22 to latch the data to memories 2a and 2b sides is provided, the time can be shortened in which one memory monopolizes the bus 3.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention provides two
The present invention relates to a data transfer circuit that transfers data to two memories.

(Prior Art) A module in a logic circuit system, for example, a CPU <
Transmission circuit)? ! For example, a multi-bus (IEEE796) is known as a bus that connects several memories (receiving circuits). In this multi-bus, the module (CPU) that sends data sends the data (
The module (memory) that outputs data (data and address) and receives the data receives the data through the receiver. The CPU on the sending side continues to issue commands while outputting data, and the memory on the receiving side receives the data.
After processing this, send a response to that effect from the sending C.
It is returned to PU. Upon receiving this response, the sending side's CPLJ
stops outputting data and also stops outputting instructions.

However, in such a device, the CPU on the sending side must continue to output data (in other words, it must continue to output instructions or addresses) until the memory on the receiving side finishes processing the received data, and the processing is completely completed. Until now, the disadvantage was that other memories could not use the bus and the bus was occupied for a long time.

(Problems to be Solved by the Invention) As mentioned above, this invention eliminates the disadvantage that one receiving circuit monopolizes the bus for a long time, and shortens the time that one receiving circuit monopolizes the bus. The purpose is to provide a data transfer circuit that can.

[Structure of the Invention] (Means for Solving the Problems) The data transfer circuit of the present invention transfers data from a transmitting circuit to a plurality of receiving circuits via a multi-bus. The data is held by a holding means in the receiving circuit, and by holding this data, the receiving circuit sends response data indicating completion of reception to the transmitting circuit.

(Operation) In this invention, the data sent from the transmitting circuit is held in the receiving circuit, and by holding this data, the receiving circuit sends response data indicating completion of reception to the transmitting circuit. be.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a data transfer circuit according to the present invention.

That is, the CPUI as a transmitting circuit, the memories 2a and 2b as receiving circuits, and the CPUI and the memory 2a as receiving circuits.
12b.

The CPtJ1 has an MPU (micro processing unit) 11 and a driver 12. When writing data into the memories 2a and 2b, the MPU 11 transfers the write data and write address to the driver 12.
The instruction data is sent to the multi-bus 3 via the multi-bus 3, and the instruction data is also output to the data bus 3. Further, when the MPLJ 11 is supplied with response data from the data bus 3, it stops outputting the corresponding write data, write address, and command data.

The main EIJ 2a (, 2b) has a RAM (Random Access Memory) 21, a latch circuit 22, and a response circuit 26 consisting of a latch signal generation circuit 23, an inverter circuit 24, and an AND circuit 25. Command data supplied from the data bus 3 is supplied to one end of the RAM 21, latch signal generation circuit 23, and AND circuit 25. Further, the address data and write data supplied from the data bus 3 are supplied to the latch circuit 22. The latch signal generating circuit 23 outputs a latch signal for a predetermined time after a predetermined time has elapsed since command data was supplied. The output of the latch signal generation circuit 23, that is, the latch signal, is supplied to the latch circuit 22, and
The signal is supplied to the other end of the AND circuit 25 via the inverter circuit 24. The AND circuit performs a logical product of the command data and the latch signal, and outputs the result, that is, a response signal from the response circuit 26.

The latch circuit 22 launches address data and write data supplied from the data bus 3 in response to a latch signal from the latch signal generation circuit 23. The address data and write data latched by the latch circuit 22 are supplied to the RAM 21.

Next, the operation of such a configuration will be described with reference to the timing charts shown in FIGS. 3 and 4.

For example, now, instruction data for the memory 2a is output from the MPU 11 of the CPU 1 to the memory 2a via the bus 3, and address data and self-programmed data are output from the driver 12 to the memory 2a via the bus 3. . Then, the command data from the bus 3 is supplied to the RAM 21, one end of the AND circuit 25, and the latch signal generation circuit 23. Further, address data and write data from the bus 3 are supplied to the latch circuit 23. As a result, a latch signal is output from the latch signal generation circuit 23 after a predetermined time period according to the above command data. This latch signal causes the latch circuit 22 to latch the address data and write data from the CPUI. The latch signal is supplied to an AND circuit 25 via an inverter circuit 24. As a result, the AND circuit 25 generates a data reception response signal ('
0' signal) to MPU 11 in CPIJl via bus 3.
Output to. Then, the MPU 11 stops outputting command data, address data, and write data to the memory 2a.

Therefore, at the falling edge of the latch signal, the latch circuit 2
2 holds data, so even if the next data is sent onto bus 3, processing continues using the held data.

Next, command data for the memory 2b is output from the MPU 11 of the CPU 1 to the memory 2b via the bus 3, and address data and write data are output from the driver 12 to the memory 2b via the bus 3. Then, the command data from the bus 3 is supplied to the RAM 21, one end of the AND circuit 25, and the latch signal generation circuit 23.

Further, address data and write data from the bus 3 are supplied to the latch circuit 23. As a result, a latch signal is output from the latch signal generation circuit 23 after a predetermined time period according to the above command data.

This latch signal causes the latch circuit 22 to
Latch the address data and 1-pack data from. The latch signal is supplied to an AND circuit 25 via an inverter circuit 24. As a result, the AND circuit 25 outputs a data reception response signal (=O-signal@) to the MPU 11 in the CPU 1 via the bus 3 based on the AND of the command data and the latch signal. Then, the ~+PIJ 11 stops outputting command data, address data, and entry data to the memory 2b.

Therefore, at the falling edge of the latch signal, the latch circuit 2
2 holds data, so even if the next data is sent onto bus 3, processing continues using the held data.

As a result, as shown in FIG. 2(a), when a command is output to the memory 2a at time t1, the memory 2a takes in and holds the data on the bus 3 by the latch signal corresponding to the command data. do.

Then, as shown in FIG. 2(b), when a command to the memory 2b is output at time t2, the memory 2b takes in and holds the data on the bus 3 by a latch signal corresponding to the command data. . At this time, the memory 2a continues processing using the data held above. In this way, the memory 2a performs the processing, and the memory 2a is sent to the bus 3 in parallel.
Data for b can be sent. This allows the time spent exclusively using the bus to be shortened.

As described above, since a latch circuit for latching data is provided on the memory side, the time that one memory occupies the bus can be reduced.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a data transfer circuit that can shorten the time that one receiving circuit monopolizes a bus.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a diagram schematically showing the overall configuration, FIG. 2 is a diagram for explaining the data transfer state, and FIGS. It is a timing chart for explaining the operation. 1...CPU (transmission circuit), 2a, 2b...memory (reception circuit), 3...bus, 11...MPU, 1
2... Driver, 21... RAM, 22... Latch circuit (holding means), 23... Latch signal generation circuit,
24... Inverter circuit, 25... AND circuit, 2
6...Response circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] In a data transfer circuit that transfers data from a transmitting circuit to a plurality of receiving circuits via a multi-bus, the data sent from the transmitting circuit is held by a holding means in the receiving circuit, and by holding this data, the receiving circuit is A data transfer circuit characterized in that the circuit is provided with means for sending response data indicating completion of reception to a transmitting circuit.